68.7.42 PWM Channel Duty Cycle Register

Only the first 16 bits (channel counter size) are significant.

Name: PWM_CDTYx
Offset: 0x0204 + x*0x20 [x=0..3]
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
 CDTY[23:16] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 CDTY[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 CDTY[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 23:0 – CDTY[23:0] Channel Duty-Cycle

Defines the waveform duty-cycle. This value must be defined between 0 and CPRD (PWM_CPRDx).