This register can be
write-protected or locked using corresponding bits in the PACCON register.
Refer to Peripheral Access Controller (PAC) for more information.
Table 10-8. Register Bit Attribute Legend
Symbol
Description
Symbol
Description
Symbol
Description
R
Readable
bit
HC
Cleared by
Hardware
(Gray
cell)
Unimplemented
W
Writable
bit
HS
Set by
Hardware
X
Bit is unknown
at Reset
C
Write to
clear
S
Software
settable bit
x
Channel
number
Name:
IVTBASE
Offset:
0x88
Bit
31
30
29
28
27
26
25
24
IVTBASE[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
IVTBASE[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
IVTBASE[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
IVTBASE[7:6]
Access
R/W
R/W
Reset
0
0
Bits 31:24 – IVTBASE[31:24]
Bits 23:16 – IVTBASE[23:16]
Bits 15:8 – IVTBASE[15:8]
Bits 7:6 – IVTBASE[7:6]
Interrupt Vector Table Base Address bits(1)
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
