10.4.26 Interrupt Enable Register 8
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | IEC8 |
| Offset: | 0xD4 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| IOMON4IE | IOMON3IE | IOMON2IE | IOMON1IE | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | |||||||||
| Reset |
Bit 22 – IOMON4IE IOM 4 Interrupt Enable bit
| Value | Description |
|---|---|
1 | Interrupt has occurred |
0 | Interrupt has not occurred |
Bit 21 – IOMON3IE IOM 3 Interrupt Enable bit
| Value | Description |
|---|---|
1 | Interrupt has occurred |
0 | Interrupt has not occurred |
Bit 20 – IOMON2IE IOM 2 Interrupt Enable bit
| Value | Description |
|---|---|
1 | Interrupt has occurred |
0 | Interrupt has not occurred |
Bit 19 – IOMON1IE IOM 1 Interrupt Enable bit
| Value | Description |
|---|---|
1 | Interrupt has occurred |
0 | Interrupt has not occurred |