6.1.3.3 AHB Bus Matrix to Fabric Interface Controller

The AHB bus matrix provides two 2-bit side band signals—driven out of the AHB bus matrix to the fabric interrupt controller to indicate which master is asserting FIC_X (X indicates FIC 0 or 1 master). The following figure shows the two FIC blocks connected to AHB bus matrix.

The FIC block provides two separate interfaces between the MSS and the FPGA fabric: the hard master (HM) and fabric master (FM). These interfaces may be configured to operate as AHB32 or APB32. Configure FIC_0 and FIC_1 interfaces in bypass mode to perform weighted round robin arbitration. For more information, see AC388: SmartFusion2 SoC FPGA - Dynamic Configuration of AHB Bus Matrix Application Note.

FIC_0_MASTER_ID and FIC_1_MASTER_ID are two signals from FIC_0 and FIC_1 to FPGA fabric that indicate the current master group accessing fabric slaves. These two signals are exposed when each FIC block interface towards the fabric is configured with the Libero SoC MSS configurator.

The following table provides the decoding of master access done by the AHB bus matrix to the fabric slave.