6.1.3.2 HBURST Support for eNVM

The AHB bus matrix only supports AHB bursts from the Cortex-M3 processor bus or from the cache to the eNVM. To support burst reads from the eNVM, you must program SW_WEIGHT_IC to be the maximum burst expected. SW_WEIGHT_IC = 32 allows a cache line to be filled from eNVM without interruption.