23.6 Fabric Interface Clocks

The fabric alignment clock controller (FACC) block in the MSS DDR clock controller is responsible for the alignment of fabric related clocks. The FACC is interfaced with MSS PLLs (MPLLs) in order to generate the various aligned clocks required by the MSS peripherals and the DDR controller in the MSS (MDDR). The lowest frequency clock, of the aligned clocks being used within the fabric, is fed to the MSS DDR clock controller and is referred to as CLK_BASE. CLK_BASE is internally multiplied and divided within the ASIC blocks in the MSS to generate higher frequency clocks that are aligned with CLK_BASE; the positive edges of CLK_BASE and derived clocks occur at the same time.

Refer to the UG0449: SmartFusion2 and IGLOO2 Clocking Resources User Guide for more details on the alignment of fabric clocks and derived clocks in the MSS.