23.9 SYSREG Control Registers for FIC_0 and FIC_1
For a detailed description of each register and bit, see System Register Block. The following table lists the control registers for FIC_0 and FIC_1 from the SYSREG block.
| Register name | Register Type | Flash Write Protect | Reset Source | Description |
|---|---|---|---|---|
| Fabric Interface Control (FIC) Register | RW-P | Register | SYSRESET_N | Control register for fabric interface |
| Software Reset Control Register | RW-P | Bit | SYSRESET_N | Generates software control interrupts to the MSS peripherals |
| MSS DDR Fabric Alignment Clock Controller (FACC) Configuration Register 1 | RW-P | Field | CC_SYSRESET_N | MSS DDR fabric alignment clock controller 1 configuration register |
| MSS DDR Clock Calibration Status | RO | – | SYSRESET_N | MSS DDR clock calibration status register |