23.4 Timing Diagrams

The timing diagrams contained in this section show AHB-Lite non-sequential transfers with 32 bits as the transfer size.

The following diagram shows the AHB-Lite bus signals from fabric interface controller to the fabric slave for a write transaction in bypass mode.

Figure 23-4. AHB-Lite Bus Signals from FIC to the Fabric Slave for a Write Transaction in Bypass Mode

The following diagram shows the AHB-Lite bus signals from the fabric interface controller to the fabric slave for a read transaction in bypass mode.

Figure 23-5. AHB-Lite Bus Signals from FIC to the Fabric Slave for a Read Transaction in Bypass Mode

The following diagram shows the AHB-Lite bus signals from the fabric interface controller to the fabric slave for write transaction in synchronous pipelined mode.

Figure 23-6. AHB-Lite Bus Signals from FIC to the Fabric Slave for a Write Transaction in Synchronous Pipelined Mode

The following diagram shows the AHB-Lite bus signals from the fabric interface controller to the fabric slave for read transaction in synchronous pipelined mode.

Figure 23-7. AHB-Lite Bus Signals from FIC to the Fabric Slave for a Read Transaction in Synchronous Pipelined Mode

The following diagram shows the AHB-Lite bus signals from the fabric master to the fabric interface controller for write transactions in bypass mode. Generation of pipelined requests depends on the efficiency of the master in the fabric to generate it.

Figure 23-8. AHB-Lite Bus Signals from Fabric Master to FIC for a Write Transaction in Bypass Mode

The following diagram shows the AHB-Lite bus signals from the fabric master to the fabric interface controller for read transactions in bypass mode. Generation of pipelined requests depends on the efficiency of the master in the fabric to generate it.

Figure 23-9. AHB-Lite Bus Signals from Fabric Master to FIC for a Read Transaction in Bypass Mode

The following diagram shows the AHB-Lite bus signals from the fabric master to the fabric interface controller for write transactions in synchronous pipelined mode. Generation of pipelined requests depends on the efficiency of the master in the fabric to generate it.

Figure 23-10. AHB-Lite Bus Signals from Fabric Master to FIC for a Write Transaction in Synchronous Pipelined Mode

The following diagram shows the AHB-Lite bus signals from the fabric master to the fabric interface controller for read transactions in synchronous pipelined mode. Generation of pipelined requests depends on the efficiency of the master in the fabric to generate it.

Figure 23-11. AHB-Lite Bus Signals from Fabric Master to FIC for a Read Transaction in Synchronous Pipelined Mode

Important: When the Fabric master accesses the MSS slave through the FIC_1 AHB-Lite slave interface, the AHB-to-AHB bridge inserts a one-cycle delay in each direction. Since these timing diagrams are at FIC interface level, the delay cannot be noticed.