11.1.4 EDAC

An internal 256 x 32 RAM in the CAN controller is EDAC protected. EDAC configurations and error counters related to the CAN are maintained in MSS system registers. For example, to enable or disable the EDAC component of the CAN, set the CAN_EDAC_EN bit (6th bit in the SYSREG EDAC_CR register) to 1. By default, EDAC is disabled (CAN_EDAC_EN is set to 0). For more information, see Table 11-5.

After power-up, the internal SRAM is not initialized and any READ to the memory location would result in an ECC error if EDAC is enabled. To initialize the SRAM, you can put the CAN controller into SRAM Test mode, initialize the SRAM, and enable the EDAC. If SECDED is enabled, Microchip recommends that the CAN controller be put into SRAM test mode and the RAM initialized with user defined known data before operation so that a future read or an uninitialized address does not trigger a SECDED error. For more information on how to put the CAN controller into SRAM test mode, see 11.5 Use Cases.