11.6.1 SYSREG Control Registers
In addition to the specific CAN registers described in this chapter, the registers found in the CAN SYSREG Control Registers also control the behavior of the CAN peripheral. For a more information on each register and bit, see System Register Block.
| Register Name | Address Offset | Register Type | Flash Write Protect | Reset Source | Description |
|---|---|---|---|---|---|
| EDAC Configuration Register | 0x38 | RW-P | Register | SYSRESET_N | Configures EDAC component of the CAN. To enable or disable the EDAC for the CAN, set the CAN_EDAC_EN bit (6th bit in this register) as follows: 0: EDAC is disabled 1: EDAC is enabled |
| EDAC Interrupt Enable Control Register | 0x78 | RW-P | Register | SYSRESET_N | Configures EDAC interrupts To set 1-bit error or 2-bit error, set the CAN_EDAC_1E_EN and CAN_EDAC_2E_N bits (the 12th and 13th bits in this register) 0: Disables the status signal 1: Enables the status signal |
| CAN EDAC Count | 0x108 | RO | SYSRESET_N | CAN EDAC count This is a 16-bit counter value in CAN. It is incremented by CAN EDAC 1-bit or 2-bit error. The counter does not roll back and stays at its maximum value. | |
| CAN EDAC Address Register | 0x11C | RO | SYSRESET_N | CAN EDAC address register CAN memory address on which 1-bit or 2-bit SECDED error occurs. | |
| EDAC Status Register | 0x190 | SW1C | SYSRESET_N | EDAC status register This status is updated by CAN when a 1-bit or 2-bit SECDED error has been detected and a single-bit error is corrected for RAM memory. | |
| Clear EDAC Counters | 0x1A4 | W1P | SYSRESET_N | Clear EDAC counters This is a pulse generated to clear the 16-bit counter value in CAN corresponding to the count value of EDAC 1-bit or 2-bit errors. This in turn clears the upper 16-bits of CAN_EDAC_CNT register. |
At power-up, the CAN_SOFTRESET bit is asserted as 1. This keeps the CAN controller in a reset state. To release the CAN controller from reset, set this bit to 0 as described in Table 11-6. If CAN_SOFTRESET is 0, the CAN controller could still be held in reset by other system reset sources. Before specifying the CAN controller configurations, release it from reset.
| Bit Number | Name | R/W | Reset Value | Description |
|---|---|---|---|---|
| 13 | CAN_SOFTRESET | R/W | 0x1 | Controls reset input to CAN Controller 0: Release CAN controller from reset. 1: Keep CAN controller in reset. |