4.6.1 Status Register Bit Definitions

The following table list the Status register bit definitions.

Table 4-21. Status Register Bit Definitions
Bit	Description
[31:29]	Value of locked state of the AHB interface. These bits contain the same information as REQACCESS[2:0].
[28:20]	Reserved
19	Command when Busy. Indicates that a command was loaded while the controller was busy and is ignored. Once set all command operations are disabled. Cleared by writing 1 to bit 2 in Table 4-25.
18	Access denied. Indicates that read or write operations were denied due to protection systems, or that an illegal command was loaded. Once set all command operations are disabled. Cleared by writing 1 to bit 1 in the Table 4-25.
17	NVM deep power-down state, indicates NVM has entered DPD mode 0: NVM operational 1: NVM In deep power-down There is delay of ~5 µs for the NVM to enter power-down and assert this bit from requesting power-down.
[16:15]	RDBUFF3 (Read data buffer 3 = Read data buffer[255:192]) ECC status (2-bit error, 1 bit corrected) 00: no error 01: 1 bit corrected 10: 2 bit detected 11: 3 or more bits detected
[14:13]	RDBUFF2 (Read data buffer 2 = Read data buffer[191:128]) ECC status (2-bit error, 1 bit corrected) 00: no error 01: 1 bit corrected 10: 2 bit detected 11: 3 or more bits detected
[12:11]	RDBUFF1 (Read data buffer 1 = Read data buffer[127:64]) ECC status (2-bit error, 1 bit corrected) 00: no error 01: 1 bit corrected 10: 2 bit detected 11: 3 or more bits detected
[10:9]	RDBUFF0 (Read data buffer 0 = Read data buffer[63:0]) ECC status (2-bit error, 1 bit corrected) 00: no error 01: 1 bit corrected 10: 2 bit detected 11: 3 or more bits detected
8	Asserted for ECC2 (2 bit error). Valid after read and read assembly buffer.
7	Asserted for ECC1 (1 bit correction). Valid after read and read assembly buffer.
6	Asserted for refresh required. Valid after program operation.
5	Asserted when write count is over threshold. Valid after program, verify, and read page status. The threshold value per eNVM page is 1000 or 10000 depending on the data retention period. For more information on programming cycles and retention time, see IGLOO® 2 FPGA and SmartFusion® 2 SoC FPGA Datasheet.
4	Asserted for program failure due to page lock. Valid after program operation.
3	Asserted for write verify failure. Valid after program operation.
2	Asserted for erase verify failure. Valid after program operation.
1	Asserted for verify failure. Valid only after verify operation.
0	NVM Ready/busy 0: Busy 1: Ready

Table 4-22. NV_FREQRNG Calculations at Different M3_CLK Frequencies for All SmartFusion® 2 Devices
Standard MSS Frequencies
M3_CLK in MHz	166	142	133	100	66	50	33
NV_FREQRNG[3:0]	0x7	0x6	0x 5	0x 4	0x 3	0x 2	0x 2
NV_FREQRNG[7:4]	0x7	0x6	0x 5	0x 4	0x 3	0x 2	0x 2
NV_FREQRNG[7:0]	0x77	0x66	0x55	0x44	0x33	0x22	0x22

Important: If M3_CLK is 166 MHz, clock period is 6.024 ns. NV_FREQRNG[3:0] = roundup(40 ns/6.024 ns) = 7.

Table 4-23. NV_PAGE_STATUS
Bit	Description
1	R/W page status select
0	Reserved

Table 4-24. INTEN[10:0]
Bit	Description
10	Command loaded when busy
9	NVM command denied by protection
8	NVM internal program operation is complete
7	ECC2 (2-bit error)
6	ECC1 (1-bit correction)
5	Refresh required
4	Write count is over threshold
3	Program failure due to page lock.
2	Reserved
1	Reserved
0	Verify failure

Table 4-25. CLRHINT[2:0]
Bit	Description
2	Clear the internal command when busy bit
1	Clear the internal access denied flag
0	Clear HINTERRUPT output

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