4.2 Functional Description

The address range of eNVM_0 is 0×60000000 to 0×6003FFFF and the address range of eNVM_1 is 0×60040000 to 0×6007FFFF. The location of eNVM_1 always follows eNVM_0 in the system memory map. The following table gives the eNVM_0 and eNVM_1 addresses for different devices.

Both eNVMs and embedded NVM controllers are identical and the eNVM controller consists of three components:

• eNVM Array
• eNVM Controller
• eNVM to AHB Controller

M3_CLK is used within the MSS to clock the AHB bus matrix. Refer to UG0449: SmartFusion2 and IGLOO2 Clocking Resources User Guide for more information on M3_CLK.

eNVM Array: The eNVM array is connected to a 25 MHz internal oscillator. This 25 MHz internal oscillator is used during device start-up to initialize the NVM controller. It is also used for eNVM program operation. For other eNVM operations (Read and Verify), the eNVM controller operates at the M3_CLK. During eNVM read operations, the NVM controller uses the NV_FREQRNG input to insert wait states to match with the eNVM array access times. The eNVM array stores the data. Table 4-2 shows the eNVM memory organization and the total size of the eNVM.

eNVM Controller: Decodes all transactions from the AHBL master and issues the commands to the eNVM array.

ECC: The error-correcting code (ECC) block in eNVM Controller performs the SECDED. The ECC stores error correction information with each block to perform SECDED on each 64-bit data word. ECC does not consume any eNVM array bits. Refer to Table 4-21 for ECC status information. ECC block in eNVM Controller is enabled by default. The user has no access to control the ECC block.

Read Data Buffer: Contains four 64-bit data words. It functions as a small cache by reading NVM data as four consecutive 64-bit data words. Data read from the eNVM is stored in read data buffer (RDBUFF) and presented to AHB read data bus (HRDATA) corresponding to HADDR.

If the data is not available, an eNVM read cycle is invoked to retrieve data from the eNVM array. To support an 8-bit fixed length wrapping burst, four eNVM read cycles are automatically invoked and data read from the eNVM is stored in RDBUFF. Read data is presented to HRDATA when the data for the current read address becomes available.

Assembly Buffer (AB): The eNVM is page-based Flash memory. Only one page of data (1,024 bits) can be written at a time. The assembly buffer stores thirty-two 32-bit data words for programming. During programming, the assembly buffer cannot be updated. If more than one page is to be written, the page programming function needs to be called as many times as the number of pages.

Write Data Buffer: The write data buffer provides a secondary 32-word data buffer. This can be updated with the next 32 words to be programmed during eNVM programming.

eNVM to AHB Controller: This block interfaces the eNVM Controller with the AHB-Lite (AHBL) master as shown in Figure 4-2.