4.5 SYSREG Control Registers
The System Control registers control eNVM behavior. These registers are located in the SYSREG section and are listed in the following tables for clarity. For more information on each register and bit, see Embedded NVM (eNVM) Controllers.
| Register Name | Register Type | Flash Write Protect | Reset Source | Description |
|---|---|---|---|---|
| Table 4-12 (0x4003800C) | RW-P | Register | sysreset_n | eNVM Configuration register. |
| Table 4-14 (0x40038010) | RW-P | Register | sysreset_n | eNVM remap Configuration register for the Cortex®-M3 processor. |
| Table 4-15 (0x40038014) | RW-P | Register | sysreset_n | eNVM remap configuration register for a soft processor in the FPGA. |
| Table 4-16 (0x40038144) | RO-U | N/A | sysreset_n | Configuration for accessibility of protected regions of eNVM_0 and eNVM_1 by different masters on the AHB bus matrix. This register gets updated by Flash bit configuration set during device programming. This configuration can be done through the System Builder using settings on the Security tab. |
| Table 4-17 (0x40038148) | RO-U | N/A | sysreset_n | Code shadow Status register. |
| Table 4-18 (0x40038158) | RO | N/A | sysreset_n | Indicates busy status for eNVM_0 and eNVM_1. |
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:17] | Reserved | 0 | — |
| 16 | ENVM_SENSE_ON | 0 | Turns On or Off the sense amps for both NVM0
and NVM1. The sense amp switching feature is useful to decrease the eNVM access time. 0: Normal Operation - The sense amp turns Off after every read cycle if an idle cycle follows. This saves power but slightly increases access time on the next read cycle. 1: The sense amp is turned ON. This increases power but decreases access times. |
| 15 | ENVM_PERSIST | 0 | Reset control for NVM0 and NVM1. 0: NVM0, NVM1 will get reset on SYSRESET_N and PORESET_N. 1: NVM0, NVM1 will get reset on PORESET_N. |
| 14 | NV_DPD1 | 0 | Deep power-down control for NVM1. 0: Normal operation 1: NVM deep power-down |
| 13 | NV_DPD0 | 0 | Deep power-down control for NVM0. 0: Normal operation 1: NVM deep power-down |
| [12:5] | NV_FREQRNG | 0x7 | Setting of NV_FREQRNG[8:5] or
NV_FREQRNG[12:9] determines the behavior of eNVM BUSY_B with respect to the AHB
Bus interface clock. It can be used to accommodate various frequencies of the
external interface clock, M3_CLK, or it can be used to advance or delay the
data capture due to variation of read access time of the NVM core. It sets the
number of wait states to match with the Cortex®-M3 or
Fabric master operating frequency for read operations. The small counter in the
NVM Controller uses this value to advance or delay the data capture before
sampling data. 0000: Not Supported 0001: Not Supported 0010: Page Read = 3, All other modes (Page program and Page verify) = 2 0011: Page Read = 4, All other modes (Page program and Page verify) = 2 0100: Page Read = 5, All other modes (Page program and Page verify) = 2 0101: Page Read = 6, All other modes (Page program and Page verify) = 3 0110: Page Read = 7, All other modes (Page program and Page verify) = 3 0111: Page Read = 8, All other modes (Page program and Page verify) = 4 1000: Page Read = 9, All other modes (Page program and Page verify) = 4 1001: Page Read = 10, All other modes (Page program and Page verify) = 4 1010: Page Read = 11, All other modes (Page program and Page verify) = 5 1011: Page Read = 12, All other modes (Page program and Page verify) = 5 1100: Page Read = 13, All other modes (Page program and Page verify) = 6 1101: Page Read = 14, All other modes (Page program and Page verify) = 6 1110: Page Read = 15, All other modes (Page program and Page verify) = 6 1111: Page Read = 16, All other modes (Page program and Page verify) = 7 NV_FREQRNG[8:5] is used for NVM0 and NV_FREQRNG[12:9] is used for NVM1. |
| 4:0 | SW_ENVMREMAPSIZE | 0x11 | Size of the segment in eNVM, which is to be remapped to location 0x00000000. This logically splits eNVM into a number of segments, each of which may be used to store a different firmware image, for example. The region sizes are shown in Table 4-13. |
| Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 | Remap Size |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | Reserved |
| 0 | 0 | 0 | 0 | 1 | Reserved |
| 0 | 0 | 0 | 1 | 0 | Reserved |
| 0 | 0 | 0 | 1 | 1 | Reserved |
| 0 | 0 | 1 | 0 | 0 | Reserved |
| 0 | 0 | 1 | 0 | 1 | Reserved |
| 0 | 0 | 1 | 1 | 0 | Reserved |
| 0 | 0 | 1 | 1 | 1 | Reserved |
| 0 | 1 | 0 | 0 | 0 | Reserved |
| 0 | 1 | 0 | 0 | 1 | Reserved |
| 0 | 1 | 0 | 1 | 0 | Reserved |
| 0 | 1 | 0 | 1 | 1 | Reserved |
| 0 | 1 | 1 | 0 | 0 | Reserved |
| 0 | 1 | 1 | 0 | 1 | 16 KB |
| 0 | 1 | 1 | 1 | 0 | 32 KB |
| 0 | 1 | 1 | 1 | 1 | 64 KB |
| 1 | 0 | 0 | 0 | 0 | 128 KB |
| 1 | 0 | 0 | 0 | 1 | 256 KB |
| 1 | 0 | 0 | 1 | 0 | 512 KB, reset value |
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:19] | Reserved | 0 | Reserved. |
| [18:1] | SW_ENVMREMAPBASE | 0 | Offset address of eNVM for remapping. SW_ENVMREMAPBASE indicates the offset within eNVM address space of the base address of the segment in eNVM, which is to be remapped to the location 0x00000000. Bit 0 of this register is defined as SW_ENVMREMAPENABLE and must be set to get the remapping done with new addresses filled in this register. |
| 0 | SW_ENVMREMAPENABLE | 0 | 0: eNVM remap not enabled. Bottom of eNVM is
mapped to address 0x00000000. 1: eNVM remap enabled. eNVM visible at 0x00000000 is a remapped segment of the eNVM. |
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:19] | Reserved | 0 | — |
| [18:1] | SW_ENVMFABREMAPBASE | 0 | Offset within eNVM address space of the base address of the segment in eNVM, which is to be remapped to location 0x00000000 for use by a soft processor in the FPGA fabric. The base address of the remapped segment of eNVM is determined by the value of this register. Bit 0 of this register is defined as SW_ENVMFABREMAPENABLE. Bit 0 must be set to remap the NVM. |
| 0 | SW_ENVMFABREMAPENABLE | 0 | 0: eNVM fabric remap not enabled for access by fabric master/soft processor. The portion of eNVM visible in the eNVM window at location 0x00000000 of a soft processor’s memory space corresponds to the memory locations at the bottom of eNVM. 1: eNVM fabric remap enabled. The portion of eNVM visible at location 0x00000000 of a soft processor’s memory space of is a remapped segment of eNVM. |
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:16] | Reserved | 0 | — |
| 15 | NVM1_UPPER_WRITE_ALLOWED | 0x1 | When set indicates that the masters who have read access can have write access to the upper protection region of eNVM1. This is updated by the user Flash row bit. |
| 14 | NVM1_UPPER_OTHERS_ACCESS | 0x1 | When set indicates that the other masters can access the upper protection region of eNVM1. This is set by the user Flash row bit. |
| 13 | NVM1_UPPER_FABRIC_ACCESS | 0x1 | When set indicates that the fabric can access the upper protection region of eNVM1. This is set by the user Flash row bit. |
| 12 | NVM1_UPPER_M3ACCESS | 0x1 | When this bit is set, it indicates that the Cortex®-M3 processor can access the upper protection region of eNVM1. This is updated by the user Flash row bit. |
| 11 | NVM1_LOWER_WRITE_ALLOWED | 0x1 | When set indicates that the masters who have read access can have write access to the lower protection region of eNVM1. This is set by the user Flash row bit. |
| 10 | NVM1_LOWER_OTHERS_ACCESS | 0x1 | When set indicates that the other masters can access the lower protection region of eNVM1. This is set by the user Flash row bit. |
| 9 | NVM1_LOWER_FABRIC_ACCESS | 0x1 | When set indicates that the fabric can access the lower protection region of eNVM1. This is set by user Flash row bit. |
| 8 | NVM1_LOWER_M3ACCESS | 0x1 | When this bit is set, it indicates that the M3 can access the lower protection region of eNVM1. This will be set by the user Flash row bit. |
| 7 | NVM0_UPPER_WRITE_ALLOWED | 0x1 | When set indicates that the masters who have read access can have write access to the upper protection region of eNVM0. This will be set by the user Flash row bit. |
| 6 | NVM0_UPPER_OTHERS_ACCESS | 0x1 | When set indicates that the other masters can access the upper protection region of eNVM0. |
| 5 | NVM0_UPPER_FABRIC_ACCESS | 0x1 | When set indicates that the fabric can access the upper protection region of eNVM0. This will be set by the user Flash row bit. |
| 4 | NVM0_UPPER_M3ACCESS | 0x1 | When this bit is set, it indicates that the M3 can access the upper protection region of eNVM0. This will be set by the user Flash row bit. |
| 3 | NVM0_LOWER_WRITE_ALLOWED | 0x1 | When set indicates that the masters who have read access can have write access to the lower protection region of eNVM0. This will be set by the user Flash row bit. |
| 2 | NVM0_LOWER_OTHERS_ACCESS | 0x1 | When set indicates that the other masters can access the lower protection region of eNVM0. This will be set by the user Flash row bit. |
| 1 | NVM0_LOWER_FABRIC_ACCESS | 0x1 | When set indicates that the fabric can access the lower protection region of eNVM0. This will be set by the user Flash row bit. |
| 0 | NVM0_LOWER_M3ACCESS | 0x1 | When this bit is set, it indicates that the M3 can access the lower protection region of eNVM0. This will be set by the user Flash row bit. |
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:1] | Reserved | 0 | — |
| 0 | CODE_SHADOW_EN | 0 | Read by the system controller during device start-up, to indicate whether the user has configured the device such that code shadowing is to be performed by system controller firmware. |
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:2] | Reserved | 0 | — |
| [1:0] | ENVM_BUSY | 0 | Active high signals indicate a busy state per eNVM for CLK-driven operations and for internal operations triggered by the program/transfer command. ENVM_BUSY[1] = Busy indication from ENVM1 ENVM_BUSY[0] = Busy indication from ENVM0 |