4.6 eNVM Control Registers
To perform any transaction with the NVM array, the Control registers must be configured appropriately as per Table 4-7.
To access or update the Control register, the AHBL master must first get access to the register set. Without access rights, all writes to the Control register will be ignored and the read will return zero from REQACC and the Table 4-21.
This access rights system ensures that while a master is programming the NVM array, no other master can interfere or see what data is being programmed.
To obtain access rights, the master writes 0x1 to the REQACC register and then reads the register to check whether access is granted. If access is granted the Control register is set.
The following table shows the base address of the eNVM Control registers for eNVM_0 and eNVM_1.
| eNVM Block | Control Registers Base Address |
|---|---|
| eNVM_0 | 0×60080000 |
| eNVM_1 | 0×600C0000 |
| OFFSET HADDR[8:0] | Register Name | Width | Type | Default | Access Rights | Description |
|---|---|---|---|---|---|---|
| 0×000-0×07F | Assembly Buffer | 1023:0 32 × 32bits |
R | — | Exclusive access to the requested master | Reads from these address will return data read from assembly buffer within the NVM array. |
| 0×080-0×0FF | WDBUFF (Write Data Buffer) | 1023:0 32 × 32bits |
R/W | 0 | Any master on AHB bus matrix | Write data buffer This register is cleared when exiting normal mode. This register is not cleared when the System Controller grabs ownership by writing 0x03 to REQACCESS. |
| 0x120 | Status | 31:0 | R | — | Any master on AHB bus matrix | See Table 4-21. |
| 0x128 | Table 4-23 | 1:0 | R/W | 0 | Exclusive access to the requested master | See Table 4-23. |
| 0x12C | NV_FREQRNG[7:0] | 7:0 | R | SYSREG | Exclusive access to the requested master | eNVM interface frequency range setting: Bits [3:0] set the number of wait cycles required for each NVM access cycles. This is read-only register. The ENVM_CR system register NV_FREQRNG field needs to be set with value as calculated below. NV_FREQRNG = roundup(40 ns / M3_CLK clock period in ns) The NV_FREQRNG[3:0] is for NVM0 wait states and NV_FREQRNG[7:4] is for NVM1 wait states. See Table 4-22 NV_FREQRNG calculations at different M3_CLK frequencies for all SmartFusion® 2 devices. Bits [7:4] are unused with the AHB-NVM block when the device has only eNVM_0. This controls the NV_FREQRNG[3:0] input on the NVMCTRL function that sets the required number of clock cycles required for NVM accesses relative to the operating frequency. |
| 0x130 | NV_DPD_B | 1-bit | R | SYSREG | Exclusive access to the requested master | NV_DPD_B[0] describes NVM deep power-down state. 0: NVM operational 1: NVM In deep power-down |
| 0x134 | NV_CE | 2-bit | R/W | 1 | Exclusive access to the requested master | NV_CE[0] = 0: NVM disabled NV_CE[0] = 1: NVM enabled NV_CE [1] = 1; The internal read cache is disabled. All reads will directly read the eNVM array, or AB space. When set NVM access latency will increase. By default this bit is set to '0'. |
| 0x140 | PAGE_LOCK_SET | 1 | R/W | 0 | Exclusive access to the requested master | PAGE_LOCK_SET[0] = 1: Page is locked. PAGE_LOCK_SET[0] = 0: Page is unlocked. If the page is locked, then before writing the page must be unlocked. |
| 0x144 | DWSIZE | 3:0 | R/W | 0 | Exclusive access to the requested master | Write size in number of double words, to be written to assembly buffer from Write Data buffer during NVM commands. See description for individual commands. 0000 = 1 dword 1111 = 16 dwords |
| 0x148 | CMD | 31:0 | R/W | 0 | Exclusive access to the requested master | Write to CMD and if command field in HWDATA decoded to be a command, then NVM command will be initiated. See description of Table 4-11: CMD register and individual commands. |
| 0x154 | INTEN[10:0] | 10:0 | R/W | 0 | Exclusive access to the requested master | Writing '1' to each bit will enable the corresponding interrupt. |
| 0x158 | Table 4-25 | 2:0 | W | 0 | Exclusive access to the requested master | Clear interrupts/flag/busy bit by writing 1 to the corresponding bit. |
| 0x1FC | REQACCESS | 2:0 | R/W | 000 | Any master on AHB bus matrix. This register can only be accessed using word, half or byte accesses to address 0×01FC. Accesses to addresses 0×1FD, 0×1FE, and 0×1F must not be used. |
Request register access When written with 0x01, it will request exclusive access. Read indicates whether access has granted or not or which entity currently has been granted access. Read Value [2:0] 0XX: No entity has access The XX value indicates who had last access. 100: System controller 101: M3 110: Fabric 111: Other master (such as, PDMA or HDMA) To release access rights, write 0x00. The System Controller may gain immediate access by writing 0x03 to this register. When access is relinquished, the WDBUFF buffer, and RDBUFF buffers are cleared. |