4.3.1 User Protectable 4K Regions

Figure 4-18. eNVM Special Sectors for the M2S050TS Device with 256 KB eNVM_0

Figure 4-19. eNVM Special Sectors for the M2S005S Device with 128 KB eNVM_0

Figure 4-20. eNVM Special Sectors for the M2S010TS, M2S025TS Devices with 256 KB eNVM_0

Figure 4-21. eNVM Special Sectors for the M2S060TS Devices with 256 KB eNVM_0

Figure 4-22. eNVM Special Sectors for the M2S090TS, M2S150TS Devices with 512 KB

The security configuration is provided as input to the eNVM Controller from system registers as per the Table 4-16 register described in Table 4-11 for configuration of upper and lower regions of NVM. The following table shows user protection regions for different masters.

Table 4-7. User Protection Regions
Master	Function
Cortex-M3 processor	Cortex-M3 processor can access the protected memory regions. Access bit defines the read accessibility. Write allowed bit indicates that the masters which have read access can also have write access.
Fabric master	FIC_0 can access the protected memory regions. Access bit defines the read accessibility. Write allowed bit indicates that the masters which have read access can also have write access.
Other masters (PDMA and HPDMA)	All other masters are allowed access. Access bit defines the read accessibility.