13.2.3.3 SPI Clock Requirements

The SPI_0 and SPI_1 peripherals are clocked by APB_0_CLK on APB bus 0, and APB_1_CLK on APB bus 1. These clocks are derived from the main MSS clock, M3_CLK. Each APB clock can be programmed individually as M3_CLK is divided by 1, 2, 4, or 8. For more information, UG0449: SmartFusion2 and IGLOO2 Clocking Resources User Guide.

The SPI clocks in master mode are derived from APB_0_CLK / APB_1_CLK. Master mode and slave mode SPI data rates depend on the APB clock, as given below.

• Master mode SPI data rate
  • Programmable from APB_X_CLK/256 to APB_X_CLK/2
  • Programmable from APB_X_CLK /65556 to APB_X_CLK /256 in powers of 2
  • Maximum data rate is APB_X_CLK/2
• Slave mode SPI data rate operates up to
  • APB_X_CLK for frame sizes (frame size ≥ 8)
  • APB_X_CLK /2 for frame sizes (frame size 4 to 7)