13.2.3.2 SPI Status at Reset

After SPI reset, the slave select (SPI_X_SS[X]) pins are held to the default values of logic High. After selecting SPI mode and enabling the SPI controller, the SPI_X_SS[x] lines are changed to the default values for each protocol. Refer to the 13.4.3.1 SPI Control Register (CONTROL). After reset, the clock out (SPI_X_CLK) is at logic Low. At reset, the FIFOs are cleared and their respective read and write pointers are set to zero. Similarly, all the internal registers of the SPI controller are reset to their default values, as explained in the 13.4.2 SPI Register Summary.

An option is provided to reset the SPI peripherals by writing to bit 9 or bit 10 in the system register, SOFT_RESET_CR. The soft resets are encoded in the following table. At power-up, the reset signals are asserted 1. It keeps the SPI peripherals in a reset state. The SPI peripheral becomes active when the bit is set to 0, as shown in the table.