2.5.4.1 Fault Types

The following table shows the types of fault, the handler used for the fault, the corresponding fault status register, and the register bit that indicates that the fault has occurred. For more information about the fault status registers, see 2.7.2.10 Configurable Fault Status Register.

Table 2-18. Faults
FaultHandlerBit nameFault status register
Bus error on a vector readHardFaultVECTTBLHardFault Status Register
Fault escalated to a HardFaultFORCED
MPU or default memory map mismatch:MemManage—
on instruction accessIACCVIOL1 MemManage Fault Status Register
on data accessDACCVIOL
during exception stackingMSTKERR
during exception unstackingMUNSKERR
Bus error:BusFault—
during exception stacking—STKERRBusFault Status Register
during exception unstacking—UNSTKERR
during instruction prefetch—IBUSERR
Precise data bus error—PRECISERR
Imprecise data bus error—IMPRECISERR
Attempt to access a coprocessorUsageFaultNOCPUsageFault Status Register
Undefined instructionUNDEFINSTR
Attempt to enter an invalid instruction set state2INVSTATE
Invalid EXC_RETURN valueUsageFaultINVPCUsageFault Status Register
Illegal unaligned load or storeUNALIGNED
Divide By 0DIVBYZERO
Note:
  1. Occurs on an access to an XN region even if the processor does not include an MPU or the MPU is disabled.
  2. Attempting to use an instruction set other than the Thumb instruction set or returns to a non load/store-multiple instruction with ICI continuation.