7.2.3 Details of Operation

After initialization, the HPDMA is ready to function in one of the two following data transfer modes:

• AHB bus matrix to MSS DDR bridge
• MSS DDR bridge to AHB bus matrix

For initiation of the above data transfer modes, a descriptor valid bit has to be set (that is, bit 16 of the Descriptor control register is asserted). If all the four descriptors are configured and set to valid, the descriptor transfer begins and executes in a round robin fashion. If any of the descriptor is paused by setting the bit 19 of Descriptor control register, the HPDMA stops the data transfer. HPDMA resumes the operation once the pause bit is reset. The pending transfers of the source and destination can be read from the Descriptor pending transfer register (HPDMADXPTR, where X is 0 to 3).

HPDMA can service the next descriptor only after the pending transfer of the current descriptor is complete. The data transfer completion interrupt is monitored using bit 20 of the Descriptor control register and bit 1 of the Descriptor status register. For more information on HPDMA registers, see 7.4.1 HPDMA Register Bit Definitions.