12.2.1 Architecture Overview

The following figure shows the functional block diagram of MMUART. The main components of MMUART include Transmit and Receive FIFOs (TX_FIFO and RX_FIFO), baud rate generator, input filters, LIN Header Detection and Auto Baud Rate Calculation block, RZI modulator and demodulator, and interrupt controller.

While transmitting data, the parallel data is written to TX_FIFO of the MMUART to transmit in serial form. While receiving data to RX_FIFO, the MMUART transforms the serial input data into parallel form to facilitate reading by the Cortex-M3 processor.

The baud rate generator contains free running counters and utilizes the asynchronous and synchronous baud rate generation circuits. The input filters in MMUART suppress the noise and spikes of incoming clock signals and serial input data based on the filter length. The RZI modulation/demodulation blocks are intended to allow for IrDA Serial Infrared (SIR) communications. The operational details of these sub blocks are explained in 12.2.4 Details of Operation.