6.6.2.1 Instruction Pipeline Overview

The pipeline stages consist of Read (RD), Execute (X[n]) and Write-Back (WB), differentiated from the equivalent CPU pipeline stages through the use of different nomenclature. The RD-stage is a single cycle operation (unless stalled). The WB-stage is always a single cycle operation. However, the execute stage will consist of as many cycles as deemed necessary for the selected instruction functional block. Most basic functions are single cycle execute operations, though more complex functions (e.g., divide) can be many cycles.

Each instruction that is issued to the FPU must be completed (or killed if speculative) in the order issued. That is, Out of Order (OoO) execution is not supported. However, as the execution time of the FPU instructions can vary considerably, in-order execution requires logic to tag each instruction as it is committed for execution, then track its progress as it flows through the instruction pipeline. Subsequent instructions will therefore be stalled until such time that earlier ones have progressed to allow for sequential, in-order execution.