6.6.2.2 Introduction to Floating Point

The IEEE standard for Floating-Point Arithmetic (IEEE 754-2008) specifies the floating-point data formats which are comprised of a Sign bit, an exponent value and a (fractional) mantissa value. The PIC32A Floating-Point Unit (FPU) supports both Single Precision (32-bit, SP) and Double Precision (64-bit, DP) operations for most (though not all) instructions. To avoid the need for another Sign bit in the exponent, the IEEE floating-point format exponent is biased by 127 (SP) or 1023 (DP). Consequently, for any datum, the required IEEE exponent value = datum exponent + bias.

In addition, the ‘1’ to the left of the most significant bit of the mantissa is implied for all numbers except subnormal numbers and is consequently referred to as the leading bit convention “hidden bit.” The mantissa is therefore a fractional value with an implied integer value of [1].
Figure 6-17. IEEE Floating-Point Data Formats and Single Precision Example

An IEEE floating-point number can therefore be represented as:

(-1)S x [1].(m (base2)) x 2(e-bias)

where:

  • ‘S’ indicates the sign of the number (same values as a signed integer value)
  • ‘e’ represents the exponent value
  • ‘m’ represents the fractional mantissa value
  • ‘bias’ is 127 (SP) or 1023 (DP)

For example, -5.75 = -(1.4375 x 22). In IEEE SP format this would be represented as:

(-1)1 x [1].4375 x 2(129-127)

or (as shown in Figure 6-17):

S = 1, exponent = 12910, mantissa = [1].4375 or:

0xC0B8 0000