For Dual 16-bit Timer mode,
the PR[31:16] bits set the count period for the second 16-bit Timer. For
32-bit Timer operation, the PR[31:0] bits set the count period for the
single 32-bit Timer. On a device Reset, the module will reset to a Dual
16-bit Timer mode. The CCPxPR Reset value of FFFFFFFF provides the maximum
count period for both timers. The PR[31:16] bits are not available in 16-bit
Output Compare modes and will read as ‘0’. The PR[31:0]
bits are not available in 32-bit Output Compare modes and will read as
‘0’.
PRL = PR[15:0] and PRH =
PR[31:16].
Table 27-9. Register Bit Attribute Legend
Symbol
Description
Symbol
Description
Symbol
Description
R
Readable
bit
HC
Cleared by
Hardware
(Gray
cell)
Unimplemented
W
Writable
bit
HS
Set by
Hardware
X
Bit is unknown
at Reset
C
Write to
clear
S
Software
settable bit
x
Channel
number
Name:
CCPxPR
Offset:
0x1B14, 0x1B44,
0x1B74, 0x1BA4
Bit
31
30
29
28
27
26
25
24
PR[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
PR[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
PR[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
PR[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bits 31:0 – PR[31:0]
Period Register bits(1,2)
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
