27.3.1 CCPx Control Register 1
Note:
- Control bit has no function in Input Capture modes.
- Control bit has no function when TRIGEN =
0. - Values greater than
‘
0011’ will cause a FIFO buffer overflow in Input Capture mode. - See Table 27-20 for the definition of Sync inputs.
- 32-bit operation is not available in Dual Edge Output Compare modes.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | CCPxCON1 |
| Offset: | 0x1B00, 0x1B30, 0x1B60, 0x1B90 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| OPSSRC | RTRGEN | OPS[3:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TRIGEN | ONESHOT | ALTSYNC | SYNC[4:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ON | SIDL | SLPEN | TMRSYNC | CLKSEL[2:0] | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TMRPS[1:0] | T32 | CCSEL | MOD[3:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 31 – OPSSRC Output Postscaler Source Select bit(1)
| Value | Description |
|---|---|
1 | Output postscaler scales module trigger output events |
0 | Output postscaler scales time base interrupt events |
Bit 30 – RTRGEN Retrigger Enable bit(2)
| Value | Description |
|---|---|
1 | Time
base can be retriggered when CCPTRIG (CCPxSTAT[7]) =
1 |
0 | Time
base may not be retriggered when CCPTRIG (CCPxSTAT[7]) =
1 |
Bits 27:24 – OPS[3:0] Time Base Interrupt/Input Capture Event Postscale Select bits(3)
| Value | Description |
|---|---|
1111 | Interrupt CPU every 16th time base period match |
1110 | Interrupt CPU every 15th time base period match |
... | |
0100 | Interrupt CPU every 5th time base period match |
0011 | Interrupt CPU every 4th time base period match or after four input capture events |
0010 | Interrupt CPU every 3rd time base period match or after three input capture events |
0001 | Interrupt CPU every 2nd time base period match or after two input capture events |
0000 | Interrupt CPU after each time base period match or each input capture event |
Bit 23 – TRIGEN CCPx Trigger Enable bit
| Value | Description |
|---|---|
1 | Trigger operation of time base is enabled |
0 | Trigger operation of time base is disabled |
Bit 22 – ONESHOT One-Shot Mode Enable bit
| Value | Description |
|---|---|
1 | One-Shot Trigger mode enabled; trigger duration set by the OSCNT[2:0] (CCPxCON3[30:28]) bits |
0 | One-Shot Trigger mode disabled |
Bit 21 – ALTSYNC Synchronization Output Select bit
| Value | Description |
|---|---|
1 | An alternate signal is used as the module synchronization output signal (see Table 27-18) |
0 | The module synchronization output signal is the time base Reset/rollover event |
Bits 20:16 – SYNC[4:0] Capture/Compare/PWM Synchronization Source Select bits(4)
| Value | Description |
|---|---|
11111 | Time base is in the Free-Running mode and rolls over at FFFF |
11110 | Time base is synchronized to source #30 |
... | |
00001 | Time base is synchronized to source #1 |
00000 | Time base is self-synchronized and rolls over at FFFF or a match with the Period register |
Bit 15 – ON Module Enable bit
| Value | Description |
|---|---|
1 | Module is enabled with the operating mode specified by the MOD[3:0] control bits |
0 | Module is disabled |
Bit 13 – SIDL Stop in Idle Mode bit
| Value | Description |
|---|---|
1 | Discontinues module operation when device enters Idle mode |
0 | Continues module operation in Idle mode |
Bit 12 – SLPEN Sleep Mode Enable bit
| Value | Description |
|---|---|
1 | Module continues to operate in Sleep modes |
0 | Module does not operate in Sleep modes |
Bit 11 – TMRSYNC Time Base Clock Synchronization bit
| Value | Description |
|---|---|
1 | Module time base clock is synchronized to internal system clocks; timing restrictions apply |
0 | Module time base clock is not synchronized to internal system clocks |
Bits 10:8 – CLKSEL[2:0] Time Base Clock Select bits
Bits 7:6 – TMRPS[1:0] Capture/Compare/PWMx Time Base Prescale Select bits
| Value | Description |
|---|---|
11 | 1:64 prescaler |
10 | 1:16 prescaler |
01 | 1:4 prescaler |
00 | 1:1 prescaler |
Bit 5 – T32 32-Bit Time Base Select bit(1,5)
| Value | Description |
|---|---|
1 | Uses 32-bit time base for selected Timer, Single Edge Output Compare or Input Capture function |
0 | Uses 16-bit time base for selected Timer, Single Edge Output Compare or Input Capture function |
Bit 4 – CCSEL Capture/Compare Mode Select bit(1)
| Value | Description |
|---|---|
1 | Module operates as an Input Capture peripheral |
0 | Module operates as an Output Compare peripheral |
Bits 3:0 – MOD[3:0] CCP Mode Select bits(1)
| Value | Description |
|---|---|
| CCSEL | 1 (Input Capture modes) |
1xxx | Reserved |
0111 | Reserved |
0110 | Reserved |
0101 | Capture every 16th rising edge |
0100 | Capture every 4th rising edge |
0011 | Capture every rising and falling edge |
0010 | Capture every falling edge |
0001 | Capture every rising edge |
0000 | Capture every rising and falling edge (Edge Detect mode) |
| CCSEL | 0 (Output Compare modes) |
1111 | External Input mode, generator disabled; source selected by the ICS[2:0] bits |
1110 | Reserved |
1101 | Reserved |
1100 | Reserved |
1011 | Reserved |
1010 | Reserved |
1001 | Reserved |
1000 | Reserved |
0111 | Reserved |
0110 | Reserved |
0101 | Dual Edge Compare mode – Buffered |
0100 | Dual Edge Compare mode |
0011 | 16-bit/32-bit Single Edge mode – toggle output on compare match |
0010 | 16-bit/32-bit Single Edge mode – drive output low on compare match |
0001 | 16-bit/32-bit Single Edge mode – drive output high on compare match |
0000 | 16-bit/32-bit Timer mode – output functions disabled |