27.3.4 CCPx Status Register

Note:
  1. This is not a physical bit location and will always read as ‘0’. A write of ‘1’ will initiate the hardware event.
  2. This bit has no effect when CLKSEL[2:0] (CCPxCON1[10:8]) = 000 or TMRSYNC = 1.
Table 27-7. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Gray cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
CWrite to clearSSoftware settable bitxChannel number
Name: CCPxSTAT
Offset: 0x1B0C, 0x1B3C, 0x1B6C, 0x1B9C

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
    PRLWIPTMRHWIPTMRLWIPRBWIPRAWIP 
Access RRRRR 
Reset 00000 
Bit 15141312111098 
      ICGARM   
Access W 
Reset 0 
Bit 76543210 
 CCPTRIGTRSETTRCLRASEVTSCEVTICDISICOVICBNE 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 20 – PRLWIP  CCPxPRL Write in Progress Status bit(2)

ValueDescription
1An update to the CCPxPRL register with the buffered contents is in progress
0An update to the CCPxPRL register is not in progress

Bit 19 – TMRHWIP  CCPxTMRH Write in Progress Status bit(2)

ValueDescription
1An update to the CCPxTMRH register with the buffered contents is in progress
0An update to the CCPxTMRH register is not in progress

Bit 18 – TMRLWIP  CCPxTMRL Write in Progress Status bit(2)

ValueDescription
1An update to the CCPxTMRL register with the buffered contents is in progress
0An update to the CCPxTMRL register is not in progress

Bit 17 – RBWIP  CCPxRB Write in Progress Status bit(2)

ValueDescription
1An update to the CCPxRB register with the buffered contents is in progress
0An update to the CCPxRB register is not in progress

Bit 16 – RAWIP  CCPxRA Write in Progress Status bit(2)

ValueDescription
1An update to the CCPxRA register with the buffered contents is in progress
0An update to the CCPxRA register is not in progress

Bit 10 – ICGARM  Input Capture Gate Arm bit(1)

A write of ‘1’ to this location will arm the Input Capture gating logic for a one-shot gate event when ICGSM[1:0] = 01 or 10. Bit location reads as ‘0’ (see Table 27-17).

Bit 7 – CCPTRIG CCPx Trigger Status bit

ValueDescription
1Timer has been triggered and is running
0Timer has not been triggered and is held in Reset

Bit 6 – TRSET  CCPx Trigger Set Request bit(1)

A write of ‘1’ to this location will request a trigger of the time base when TRIGEN = 1. The bit will clear automatically after the trigger event has been generated, allowing a new trigger event to be requested.

Bit 5 – TRCLR  CCPx Trigger Clear Request bit(1)

A write of ‘1’ to this location will request a trigger cancellation when TRIGEN = 1 and CCPTRIG = 1. Bit clears automatically after the cancellation has completed, allowing a new cancellation to be requested.

Bit 4 – ASEVT CCPx Auto-Shutdown Event Status/Control bit

ValueDescription
1A shutdown event is in progress; CCP outputs are in the Shutdown state
0CCP outputs operate normally

Bit 3 – SCEVT Single Edge Compare Event Status bit

ValueDescription
1A single edge Compare event has occurred
0A single edge Compare event has not occurred

Bit 2 – ICDIS Input Capture Disable bit

ValueDescription
1Event on Input Capture pin does not generate a capture event
0Event on Input Capture pin will generate a capture event

Bit 1 – ICOV Input Capture Buffer Overflow Status bit

ValueDescription
1The Input Capture FIFO buffer has overflowed
0The Input Capture FIFO buffer has not overflowed

Bit 0 – ICBNE Input Capture Buffer Status bit

ValueDescription
1Input Capture buffer has data available
0Input Capture buffer is empty