TMR[31:16] will be available
when operating in a valid 32-bit Operating mode, or the dual 16-bit Time
Base mode. TMR[31:16] will read as ‘0’ when operating in
all other modes.
All writes to CCPxTMR are
buffered for atomic update operation. The CCPxTMR value is not updated until
the uppermost byte of the timer is written. If the timer clock source is
asynchronous, user software must monitor the status bits to ensure the prior
write has completed before performing another write.
TMRL = TMR[15:0] and TMRH =
TMR[31:16].
Table 27-8. Register Bit Attribute Legend
Symbol
Description
Symbol
Description
Symbol
Description
R
Readable
bit
HC
Cleared by
Hardware
(Gray
cell)
Unimplemented
W
Writable
bit
HS
Set by
Hardware
X
Bit is unknown
at Reset
C
Write to
clear
S
Software
settable bit
x
Channel
number
Name:
CCPxTMR
Offset:
0x1B10, 0x1B40,
0x1B70, 0x1BA0
Bit
31
30
29
28
27
26
25
24
TMR[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
TMR[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
TMR[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
TMR[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bits 31:0 – TMR[31:0]
32-bit Time Base Value bits(1,2,3)
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
