27.3.3 CCPx Control Register 3
Note:
- ONESHOT (CCPxCON1[22]) must be set for the OSCNT[2:0] bits to be effective.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | CCPxCON3 |
| Offset: | 0x1B08, 0x1B38, 0x1B68, 0x1B98 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| OETRIG | OSCNT[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| POLACE | PSSACE[1:0] | ||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | |||||||||
| Reset |
Bit 31 – OETRIG Output Enable on Trigger Control bit
| Value | Description |
|---|---|
1 | For
Triggered mode (TRIGEN = 1), module does not drive enabled
output pins until triggered |
0 | Normal output pin operation |
Bits 30:28 – OSCNT[2:0] One-Shot Count bits(1)
| Value | Description |
|---|---|
111 | Extend one-shot trigger event 7 time base count cycles (8 time base periods total) |
110 | Extend one-shot trigger event 6 time base count cycles (7 time base periods total) |
101 | Extend one-shot trigger event 5 time base count cycles (6 time base periods total) |
100 | Extend one-shot trigger event 4 time base count cycles (4 time base periods total) |
011 | Extend one-shot trigger event 3 time base count cycles (4 time base periods total) |
010 | Extend one-shot trigger event 2 time base count cycles (3 time base periods total) |
001 | Extend one-shot trigger event 1 time base count cycle (2 time base periods total) |
000 | Do not extend one-shot trigger event |
Bit 21 – POLACE CCP Output Pin, OCxA, Polarity Control bit
| Value | Description |
|---|---|
1 | Output pin polarity is active-low |
0 | Output pin polarity is active-high |
Bits 19:18 – PSSACE[1:0] PWM Output Pin, OCxA, Shutdown State Control bits
| Value | Description |
|---|---|
11 | Pins are driven active when a shutdown event occurs |
10 | Pins are driven inactive when a shutdown event occurs |
0x | Pins are tri-stated when a shutdown event occurs |