27.3.2 CCPx Control Register 2

Note:

This bit has no effect in Timer modes, Output Compare modes or PWM modes. A write to the ICGARM (CCPxSTAT[10]) bit will re-arm the one-shot gating circuit when ICGSM = 01 or ICGSM = 10.
This bit has no affect for Timer gating or Input Capture gating functions.

Table 27-5. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	CCPxCON2
Offset:	0x1B04, 0x1B34, 0x1B64, 0x1B94


Bit	31	30	29	28	27	26	25	24
	OENSYNC							OCAEN
Access	R/W							R/W
Reset	0							0


Bit	23	22	21	20	19	18	17	16
	ICGSM[1:0]			AUXOUT[1:0]		ICS[2:0]
Access	R/W	R/W		R/W	R/W	R/W	R/W	R/W
Reset	0	0		0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	PWMRSEN	ASDGM		SSDG
Access	R/W	R/W		R/W
Reset	0	0		0


Bit	7	6	5	4	3	2	1	0
	ASDG[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 31 – OENSYNC Output Enable Synchronization bit

Value	Description
`1`	Update by output enable bits occurs on the next time base Reset or rollover
`0`	Update by output enable bits occurs immediately

Bit 24 – OCAEN Output Enable/Steering Control bits

Value	Description
`1`	OCx pin is controlled by the CCP module and produces an Output Compare or PWM signal
`0`	OCx pin is not controlled by the CCP module; the pin is available to the port logic or another peripheral multiplexed on the pin

Bits 23:22 – ICGSM[1:0] Input Capture Gating Source Mode Control bits⁽¹⁾

Value	Description
`11`	Reserved
`10`	One-Shot mode; falling edge from gating source will disable future capture events (CDIS = `1`)
`01`	One-Shot mode; rising edge from gating source will enable future capture events (CDIS = `0`)
`00`	Level Sensitive mode; a high level from gating source will enable future capture events; a low level will disable future capture events

Bits 20:19 – AUXOUT[1:0] Auxiliary Output Signal Selection bits

Value	Description
`11`	Signal output depends on module operating mode (see Table 27-19)
`10`	Signal output depends on module operating mode (see Table 27-19)
`01`	Signal output depends on module operating mode (see Table 27-19)
`00`	No signal output on aux_out

Bits 18:16 – ICS[2:0] Input Capture Source Select bits

See Table 27-3.

Bit 15 – PWMRSEN CCPx Output Compare Restart Enable bit

Value	Description
`1`	ASEVT (CCPxSTAT[4]) bit clears automatically at the beginning of the next Output Compare period, after the shutdown input has ended
`0`	ASEVT (CCPxSTAT[4]) bit must be cleared in software to resume Output Compare activity on output pins

Bit 14 – ASDGM CCPx Auto-Shutdown/Gate Control bit⁽¹⁾

Value	Description
`1`	Wait until next time base Reset or rollover for an Output Compare pin shutdown to occur
`0`	Output Compare pin shutdown event occurs immediately

Bit 12 – SSDG CCPx Software Shutdown/Gate Control bit

Value	Description
`1`	Manually force auto-shutdown, Timer clock gate or Input Capture signal gate event (setting of ASDGM bit still applies)
`0`	Normal module operation

Bits 7:0 – ASDG[7:0] CCPx Auto-Shutdown/Gating Source Enable bits

Refer to Table 27-17 for Auto-Shutdown and Gating Sources.

Value	Description
`1`	ASDG source n is enabled
`0`	ASDG source n is disabled

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