27.4.4.2.6 CCPxTMRL = CCPxRB and CCPxRA = 0

In Sync operation, if CCPxRA is 0000h, the OCx output is asserted on the first clock after the Timer Reset (CCPxTMRL = 0001h). It remains asserted until the value of CCPxRB matches the timer period (when the input selected by SYNC[4:0] is asserted). At this point, the OCx output is deasserted and the CCPxIF is generated on the falling edge (Figure 27-18).

Figure 27-18. Timing for Dual Edge Compare (CCPxRA = 0000h, CCPxRB = Timer Period)