18.4.3.1 Sampling Time Requirements

The analog input model of the ADC is illustrated in Figure 18-2.

It takes time to charge the Holding Capacitor (CHOLD) to the input signal level through the source and internal device resistance.

The total acquisition time for the Analog-to-Digital conversion is a function of the Holding Capacitor (CHOLD) charge time. For the ADC module to meet its specified accuracy, the Holding Capacitor (CHOLD) must be allowed to fully charge to the voltage level on the analog input pin. The Signal Source Impedance (RS) and the Interconnect Impedance (RIC) combine to directly affect the time required to charge the CHOLD. The combined impedance (RTOTAL = RS + RIC) must therefore be small enough to fully charge the Holding Capacitor within the selected sample time. To charge the CHOLD with 0.5 LSB error, the sampling time should be more than the time defined by the Minimum Sampling Time equation below.

Equation 18-1. Minimum Sampling Time
TSAMPLING = RTOTAL x CHOLD x ln(2(RESOLUTION + 1)) or

For 12-Bit Resolution:

TSAMPLING = 9 x RTOTAL x CHOLD

Figure 18-2. ADC Input Model
Note:
  1. The CPIN value depends on the device package and is not tested.
  2. See RIC value in the Electrical Specifications.
  3. See CHOLD value in the Electrical Specifications.