6.2.5 Core Mode Control Register⁽¹⁾

Table 6-5. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Note:

The Core Control register (CORCON) has bits that control the operation of the DSP multiplier hardware.

Name:	CORCON
Offset:	0x010


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
				US
Access				R/W
Reset				0


Bit	7	6	5	4	3	2	1	0
	SATA	SATB	SATDW	ACCSAT			RND	IF
Access	R/W	R/W	R/W	R/W			R/W	R/W
Reset	0	0	0	0			0	0

Bit 12 – US Unsigned or Signed Multiplier Mode Select bit

Value	Description
`1`	Unsigned mode enabled for DSP ops
`0`	Signed mode enabled for DSP ops

Bit 7 – SATA AccA Saturation Enable bit

Value	Description
`1`	Accumulator A saturation enabled
`0`	Accumulator A saturation disabled

Bit 6 – SATB AccB Saturation Enable bit

Value	Description
`1`	Accumulator B saturation enabled
`0`	Accumulator B saturation disabled

Bit 5 – SATDW Data Space Write from DSP Engine Saturation Enable bit

Value	Description
`1`	Data Space write saturation enabled
`0`	Data Space write saturation disabled

Bit 4 – ACCSAT Accumulator Saturation Mode Select bit

Value	Description
`1`	9.63 saturation (super saturation)
`0`	1.63 saturation (normal saturation)

Bit 1 – RND Rounding Mode Select bit

Value	Description
`1`	Biased (conventional) rounding enabled
`0`	Unbiased (convergent) rounding enabled

Bit 0 – IF Integer or Fractional Multiplier Mode Select bit

Value	Description
`1`	Integer mode is enabled for DSP multiply
`0`	Fractional mode is enabled for DSP multiply

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