1.3.2.2 CoreDMA and UART Subsystem

The CoreDMA_IO_CTRL SmartDesign implements fabric registers, CoreDMA4DMA IP initialization and UART_SD. See the following figure.

The axi4dma_init logic initiates the CoreDMA through the AXI4Lite interface to perform the DMA as per commands from GUI. The axi_io_ctrl block receives commands from PCIe BAR space and controls the IOs or axi4dma_init logic.

The CoreAXI4DMAController IP is configured for 64-bit AXI4 data width, and to generate interrupts for descriptor0 and descriptor1. Descriptor0 is used for—DDR3L to DDR4, DDR3L to LSRAM and DDR4 to LSRAM DMA and descriptor1 is used for—DDR4 to DDR3L, LSRAM to DDR3L and LSRAM to DDR4 DMA.

The following figure shows the CoreDMA_IO_CTRL SmartDesign.

The UART_SD SmartDesign implements logic required to communicate with UART IF, see the following figure. The cmd_ctrlr block receives commands from UART and triggers the logic to perform CoreDMA/DDR memory initialization. The pattern_gen_checker block initializes the DDR memory with the specified pattern and compares against the specified pattern.