1.3.2.1 PCIe EP Subsystem

The PCIe_EP SmartDesign implements PCIe EndPoint and its clocking scheme, as shown in the following figure. It also includes the sw_debounce module, which is used to suppress bounces from on-board push buttons and to generate a pulse to the PCIe controller interrupt line.

The PCIE core is configured as an EndPoint with maximum link speed and maximum link width—Gen2 (5.0 Gbps) link speed and × 4 link width. The Simulation Level in the configurator is set to BFM to simulate the design using PCIe BFM script. The PCIe fabric interface is always the same regardless of the link width or lane rate. The APB interface is enabled to access the PCIe DMA and Address translation registers.

The following two BARs are configured in 64-bit:

  • BAR0: Accesses the PCIe DMA, address translation and interrupt registers through the PCIe controller's APB interface. The address translation register associated with BAR0 is configured to translate the BAR0 address to the PCIe APB IF base address (0x0300_0000).
  • BAR2: Accesses the fabric control registers and AXI LSRAM, DDR3L and DDR4 memories. By default, the address translation register associated with BAR2 is configured to access the fabric control registers (0x1000_0000). To access the LSRAM, DDR3L and DDR4 memories, the driver on the host PC configures the BAR2 address translation register (TRSL_ADDR) to LSRAM (0x3000_0000)/DDR3L (0x2000_0000)/DDR4 (0x4000_0000) memory base address using the PCIe APB IF through BAR0.
Figure 1-5. PCIe_EP SmartDesign

The PCIe_TL_CLK SmartDesign implements PCIe TL CLK for PolarFire devices, see Figure 1-6. PCIe TL CLK must be connected to CLK_125 MHz of Tx PLL. In PolarFire devices, TL CLK is available only after PCIe initialization. The 80 MHz clock is derived from the on-chip 160 MHz oscillator to drive the TL CLK during PCIe initialization. The NGMUX is used to switch this clock to the required CLK_125 MHz after PCIe initialization. The BANK 0, BANK 1 and BANK 7 calibration status signals of PF Initialization Monitor IP is used to generate CALIB_DONE signal, which is used for DDR3L/DDR4 reset.

Figure 1-6. PCIe_TL_CLK SmartDesign