37.4.36 I3CxDSTAT0
Note:
- This Target module does not support Activity Status, hence the meaning of these bits is up to the vendor to define and is to be communicated to the Controller through a private agreement.
- This bit is set alongside BUSEIF bit when a bus error is detected.
- This byte is the lower byte read by the Controller during a GETSTATUS CCC.
- To guarantee expected behavior, this register should only be written when the
module is disabled (EN =
0).
| Name: | I3CxDSTAT0 |
| Address: | 0x0AA, 0x0DD |
Device Status 0
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ACTMODE[1:0] | PERR | INTPEND[3:0] | |||||||
| Access | R/W | R/W | R/HS/HC | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bits 7:6 – ACTMODE[1:0] Activity Mode (1)
Bit 5 – PERR Protocol Error(2)
| Value | Description |
|---|---|
| 1 | The Target detected a protocol error since the last Status read (the bit self-clears after the Controller successfully reads the Target’s status) |
| 0 | The Target has not detected a protocol error since the last Status read |
Bits 3:0 – INTPEND[3:0] Pending Interrupt
| Value | Description |
|---|---|
| other | The interrupt number of the highest priority pending interrupt |
| 0 | There is no pending interrupt |