10.2.7.1 Fusion Static PLL Functionality

The input clock, fin, is first passed through the adjustable divider (FINDIV) prior to application to the PLL core phase detector's PLLFIN input.

The feedback signal, to which fin is compared, can be selected from several sources, giving the Static PLL its flexibility. All sources of the feedback signal can be divided by 1, 2, 3, …128 in divider FBDIV. This has the effect of multiplying the input signal. The source signals are:

• The VCO output signal, with 0o phase shift and zero additional time delay
• A delayed version of the VCO output, in selectable increments of 200 ps, up to 6.735 ns
• An external feedback signal from I/O

Each of the feedback source signals mentioned previously can be further delayed by a fixed amount designed to emulate the delay through the chip’s clock tree. This allows for clock-line de-skewing operations.

When the loop has acquired lock, the Lock Detect signal is asserted. This signal is available to the logic core through the output port LOCK.

Once locked, the various output combinations are available to the Global lines.