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21
SmartTime
21.10
Generating Timing Reports
21.10.3
Understanding Timing Reports
21.10.3.3
Path Sections
21.10.3.3.1
Clock Domains
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SmartTime
21
Introduction
21.1
Design Flows with SmartTime
21.2
Starting and Closing SmartTime
21.3
SmartTime Components
21.4
SmartTime Constraint Scenario
21.5
Setting SmartTime Options
21.6
SmartTime Tutorial
21.7
SmartTime Constraints Editor
21.8
SmartTime Timing Analyzer
21.9
Advanced Timing Analysis
21.10
Generating Timing Reports
21.10.1
Types of Reports
21.10.2
Generating a Timing Report
21.10.3
Understanding Timing Reports
21.10.3.1
Header
21.10.3.2
Summary
21.10.3.3
Path Sections
21.10.3.3.1
Clock Domains
21.10.3.3.2
Register to Register Set
21.10.3.3.3
Input to Register Set
21.10.3.3.4
Register to Output Set
21.10.3.3.5
Inter-clock Domain
21.10.3.3.6
Pin to Pin
21.10.3.3.7
Input to Output Set
21.10.3.3.8
Expanded Paths
21.10.4
Generating a Timing Violation Report
21.10.5
Understanding Timing Violation Reports
21.10.6
Generating a Constraints Coverage Report
21.10.7
Understanding Constraints Coverage Reports
21.10.8
Generating a Bottleneck Report
21.10.9
Understanding Bottleneck Reports
21.10.10
Generating a Datasheet Report
21.10.11
Understanding Datasheet Reports
21.10.12
Generating a Combinational Loop Report
21.10.13
Understanding Combinational Loop Reports
21.11
Timing Concepts
21.12
Dialog Boxes
21.13
Menus, Tools, and Shortcut Keys
21.14
Data Change History – SmartTime
21.15
Constraints by File Format - SDC Command Reference
21.16
Design Object Access Commands
21.17
Glossary
21.18
Revision History
21
Microchip FPGA Support
21
Microchip Information
22
Timer
23
VHDL Vital Simulation
24
Verilog Simulation
25
Technical Support
26
About Microchip
21.10.3.3.1 Clock Domains
The paths are organized by clock domain.
Rev: A
