21.1.1 Timer1 Control Register
- When Timer1 is enabled in External Synchronous Counter mode (TCS =
1, TSYNC =1, TON =1), any attempts by user software to write to the TMR1 register are ignored.
| Name: | T1CON |
| Offset: | 0x100 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TON | SIDL | TMWDIS | TMWIP | PRWIP | TECS[1:0] | ||||
| Access | R/W | R/W | R/W | R | R | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TGATE | TCKPS[1:0] | TSYNC | TCS | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bit 15 – TON Timer1 On bit(1)
| Value | Description |
|---|---|
1 |
Starts 16-bit Timer1 |
0 |
Stops 16-bit Timer1 |
Bit 13 – SIDL Timer1 Stop in Idle Mode bit
| Value | Description |
|---|---|
1 |
Discontinues module operation when device enters Idle mode |
0 |
Continues module operation in Idle mode |
Bit 12 – TMWDIS Asynchronous Timer1 Write Disable bit
| Value | Description |
|---|---|
1 |
Timer writes are ignored while a posted write to TMR1 or PR1 is synchronized to the asynchronous clock domain |
0 |
Back-to-back writes are enabled in Asynchronous mode |
Bit 11 – TMWIP Asynchronous Timer1 Write in Progress bit
| Value | Description |
|---|---|
1 |
Write to the timer in Asynchronous mode is pending |
0 |
Write to the timer in Asynchronous mode is complete |
Bit 10 – PRWIP Asynchronous Period Write in Progress bit
| Value | Description |
|---|---|
1 |
Write to the Period register in Asynchronous mode is pending |
0 |
Write to the Period register in Asynchronous mode is complete |
Bits 9:8 – TECS[1:0] Timer1 Extended Clock Select bits
| Value | Description |
|---|---|
11 |
FRC clock |
10 |
2 TCY |
01 |
TCY |
00 |
External Clock comes from the T1CK pin |
Bit 7 – TGATE Timer1 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
| Value | Description |
|---|---|
1 |
Gated time accumulation is enabled |
0 |
Gated time accumulation is disabled |
Bits 5:4 – TCKPS[1:0] Timer1 Input Clock Prescale Select bits
| Value | Description |
|---|---|
11 |
1:256 |
10 |
1:64 |
01 |
1:8 |
00 |
1:1 |
Bit 2 – TSYNC Timer1 External Clock Input Synchronization Select bit(1)
When TCS = 0:
This bit is ignored.
When TCS =1:| Value | Description |
|---|---|
1 |
Synchronizes the External Clock input |
0 |
Does not synchronize the External Clock input |
Bit 1 – TCS Timer1 Clock Source Select bit(1)
| Value | Description |
|---|---|
1 |
External Clock source selected by TECS[1:0] |
0 |
Internal peripheral clock (FP) |