3.4.1 Programmer's Model

The programmer’s model for the dsPIC33CK512MPT608 family is shown in Figure 3-2. All registers in the programmer’s model are memory-mapped and can be manipulated directly by instructions. Table 3-1 lists a description of each register.

In addition to the registers contained in the programmer’s model, the dsPIC33CK512MPT608 devices contain control registers for Modulo Addressing, Bit-Reversed Addressing and interrupts. These registers are described in subsequent sections of this document.

All registers associated with the programmer’s model are memory-mapped, as shown in Figure 3-2 .

Table 3-1. Programmer’s Model Register Descriptions
Register(s) Name	Description
W0 through W15⁽¹⁾	Working Register Array
W0 through W14⁽¹⁾	Alternate Working Register Array 1
W0 through W14⁽¹⁾	Alternate Working Register Array 2
W0 through W14⁽¹⁾	Alternate Working Register Array 3
W0 through W14⁽¹⁾	Alternate Working Register Array 4
ACCA, ACCB	40-Bit DSP Accumulators (Additional 4 Alternate Accumulators)
PC	23-Bit Program Counter
SR	ALU and DSP Engine STATUS Register
SPLIM	Stack Pointer Limit Value Register
TBLPAG	Table Memory Page Address Register
DSRPAG	Extended Data Space (EDS) Read Page Register
RCOUNT	`REPEAT` Loop Counter Register
DCOUNT	`DO` Loop Counter Register
DOSTARTH, DOSTARTL⁽²⁾	`DO` Loop Start Address Register (High and Low)
DOENDH, DOENDL	`DO` Loop End Address Register (High and Low)
CORCON	Contains DSP Engine, `DO` Loop Control and Trap Status bits
Note: Memory-mapped W0 through W14 represent the value of the register in the currently active CPU context. The DOSTARTH and DOSTARTL registers are read-only.

Figure 3-2. Programmer’s Model