3.4.1 Programmer's Model

The programmer’s model for the dsPIC33CK512MPT608 family is shown in Figure 3-2. All registers in the programmer’s model are memory-mapped and can be manipulated directly by instructions. Table 3-1 lists a description of each register.

In addition to the registers contained in the programmer’s model, the dsPIC33CK512MPT608 devices contain control registers for Modulo Addressing, Bit-Reversed Addressing and interrupts. These registers are described in subsequent sections of this document.

All registers associated with the programmer’s model are memory-mapped, as shown in Figure 3-2 .

Table 3-1. Programmer’s Model Register Descriptions
Register(s) NameDescription
W0 through W15(1)Working Register Array
W0 through W14(1)Alternate Working Register Array 1
W0 through W14(1)Alternate Working Register Array 2
W0 through W14(1)Alternate Working Register Array 3
W0 through W14(1)Alternate Working Register Array 4
ACCA, ACCB40-Bit DSP Accumulators (Additional 4 Alternate Accumulators)
PC23-Bit Program Counter
SRALU and DSP Engine STATUS Register
SPLIMStack Pointer Limit Value Register
TBLPAGTable Memory Page Address Register
DSRPAGExtended Data Space (EDS) Read Page Register
RCOUNTREPEAT Loop Counter Register
DCOUNTDO Loop Counter Register
DOSTARTH, DOSTARTL(2)DO Loop Start Address Register (High and Low)
DOENDH, DOENDLDO Loop End Address Register (High and Low)
CORCONContains DSP Engine, DO Loop Control and Trap Status bits
Note:
  1. Memory-mapped W0 through W14 represent the value of the register in the currently active CPU context.
  2. The DOSTARTH and DOSTARTL registers are read-only.
Figure 3-2. Programmer’s Model