4.4.1 Paged Memory Scheme

The dsPIC33CK512MPT608 architecture extends the available Data Space through a paging scheme, which allows the available Data Space to be accessed using MOV instructions in a linear fashion for pre- and post-modified Effective Addresses (EAs). The upper half of the base Data Space address is used in conjunction with the Data Space Read Page (DSRPAG) register to form the Program Space Visibility (PSV) address.

The Data Space Read Page (DSRPAG) register is located in the SFR space. When DSRPAG[9] = 1 and the base address bit, EA[15] = 1, the DSRPAG[8:0] bits are concatenated onto EA[14:0] to form the 24-bit PSV read address.

The paged memory scheme provides access to multiple 32-Kbyte windows in the PSV memory. The Data Space Read Page (DSRPAG) register, in combination with the upper half of the Data Space address, can provide up to 8 Mbytes of PSV address space. The paged data memory space is shown in Figure 4-8.

The Program Space (PS) can be accessed with a DSRPAG of 0x200 or greater. Only reads from PS are supported using the DSRPAG.

Figure 4-7. Program Space Visibility (PSV) Read Address Generation

Note: DS read access when DSRPAG = 0x000 will force an address error trap.

Figure 4-8. Paged Data Memory Space

When a PSV page overflow or underflow occurs, EA[15] is cleared as a result of the register indirect EA calculation. An overflow or underflow of the EA in the PSV pages can occur at the page boundaries when:

The initial address, prior to modification, addresses the PSV page
The EA calculation uses Pre- or Post-Modified Register Indirect Addressing; however, this does not include Register Offset Addressing

In general, when an overflow is detected, the DSRPAG register is incremented and the EA[15] bit is set to keep the base address within the PSV window. When an underflow is detected, the DSRPAG register is decremented and the EA[15] bit is set to keep the base address within the PSV window. This creates a linear PSV address space, but only when using Register Indirect Addressing modes.

Exceptions to the operation described above arise when entering and exiting the boundaries of Page 0 and PSV spaces. Table 4-2 lists the effects of overflow and underflow scenarios at different boundaries.

In the following cases, when overflow or underflow occurs, the EA[15] bit is set and the DSRPAG is not modified; therefore, the EA will wrap to the beginning of the current page:

Register Indirect with Register Offset Addressing
Modulo Addressing
Bit-Reversed Addressing

Table 4-2. Overflow and Underflow Scenarios at Page 0 and PSV Space Boundaries^(2,3,4)
O/U, R/W	Operation	Before			After
O/U, R/W	Operation	DSRPAG	DS EA[15]	Page Description	DSRPAG	DS EA[15]	Page Description
O, Read	`[++Wn]` or `[Wn++]`	DSRPAG = 0x2FF	`1`	PSV: Last lsw page	DSRPAG = 0x300	`1`	PSV: First MSB page
O, Read	`[++Wn]` or `[Wn++]`	DSRPAG = 0x3FF	`1`	PSV: Last MSB page	DSRPAG = 0x3FF	`0`	See Note 1
U, Read	`[--Wn]` or `[Wn--]`	DSRPAG = 0x001	`1`	PSV page	DSRPAG = 0x001	`0`	See Note 1
U, Read		DSRPAG = 0x200	`1`	PSV: First lsw page	DSRPAG = 0x200	`0`	See Note 1
U, Read		DSRPAG = 0x300	`1`	PSV: First MSB page	DSRPAG = 0x2FF	`1`	PSV: Last lsw page
Legend: O = Overflow, U = Underflow, R = Read, W = Write Note: The Register Indirect Addressing now addresses a location in the base Data Space (0x0000-0x8000). An EDS access, with DSRPAG = 0x000, will generate an address error trap. Only reads from PS are supported using DSRPAG. Pseudolinear Addressing is not supported for large offsets.