19.5.3 I2Cx Status Register
Legend: C = Clearable bit; HS = Hardware Settable bit; HSC = Hardware Settable/Clearable bit
| Name: | I2CxSTAT |
| Offset: | 0x204, 0x220, 0xF60 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ACKSTAT | TRSTAT | ACKTIM | BCL | GCSTAT | ADD10 | ||||
| Access | R/HSC | R/HSC | R/HSC | R/C/HSC | R/HSC | R/HSC | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| IWCOL | I2COV | D/A | P | S | R/W | RBF | TBF | ||
| Access | R/C/HS | R/C/HS | R/HSC | R/HSC | R/HSC | R/HSC | R/HSC | R/HSC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 15 – ACKSTAT Acknowledge Status bit (updated in all Host and Client modes)
| Value | Description |
|---|---|
1 |
Acknowledge was not received from Client |
0 |
Acknowledge was received from Client |
Bit 14 – TRSTAT Transmit Status bit (when operating as I2C Host; applicable to Host transmit operation)
| Value | Description |
|---|---|
1 |
Host transmit is in progress (eight bits + ACK) |
0 |
Host transmit is not in progress |
Bit 13 – ACKTIM Acknowledge Time Status bit (valid in I2C Client mode only)
| Value | Description |
|---|---|
1 |
Indicates I2C bus is in an Acknowledge sequence, set on 8th falling edge of SCLx clock |
0 |
Not an Acknowledge sequence, cleared on 9th rising edge of SCLx clock |
Bit 10 – BCL Bus Collision Detect bit
0)| Value | Description |
|---|---|
1 |
A bus collision has been detected during a Host or Client transmit operation |
0 |
No bus collision has been detected |
Bit 9 – GCSTAT General Call Status bit (cleared after Stop detection)
| Value | Description |
|---|---|
1 |
General call address was received |
0 |
General call address was not received |
Bit 8 – ADD10 10-Bit Address Status bit (cleared after Stop detection)
| Value | Description |
|---|---|
1 |
10-bit address was matched |
0 |
10-bit address was not matched |
Bit 7 – IWCOL I2Cx Write Collision Detect bit
| Value | Description |
|---|---|
1 |
An attempt to write to the I2CxTRN register failed because the I2C module is busy; must be cleared in software |
0 |
No collision |
Bit 6 – I2COV I2Cx Receive Overflow Flag bit
| Value | Description |
|---|---|
1 |
A byte was received while the I2CxRCV register is still holding the previous byte; I2COV is a “don’t care” in Transmit mode, must be cleared in software |
0 |
No overflow |
Bit 5 – D/A Data/Address bit (when operating as I2C Client)
| Value | Description |
|---|---|
1 |
Indicates that the last byte received was data |
0 |
Indicates that the last byte received or transmitted was an address |
Bit 4 – P I2Cx Stop bit
Updated when Start, Reset or Stop is detected; cleared when the I2C
module is disabled, I2CEN = 0.
| Value | Description |
|---|---|
1 |
Indicates that a Stop bit has been detected last |
0 |
Stop bit was not detected last |
Bit 3 – S I2Cx Start bit
Updated when Start, Reset or Stop is detected; cleared when the I2C
module is disabled, I2CEN = 0.
| Value | Description |
|---|---|
1 |
Indicates that a Start (or Repeated Start) bit has been detected last |
0 |
Start bit was not detected last |
Bit 2 – R/W Read/Write Information bit (when operating as I2C Client)
| Value | Description |
|---|---|
1 |
Read: Indicates the data transfer is output from the Client |
0 |
Write: Indicates the data transfer is input to the Client |
Bit 1 – RBF Receive Buffer Full Status bit
| Value | Description |
|---|---|
1 |
Receive is complete, I2CxRCV is full |
0 |
Receive is not complete, I2CxRCV is empty |
Bit 0 – TBF Transmit Buffer Full Status bit
| Value | Description |
|---|---|
1 |
Transmit is in progress, I2CxTRN is full (eight bits of data) |
0 |
Transmit is complete, I2CxTRN is empty |