19.5.1 I2Cx Control Register Low

Note:
  1. Automatically cleared to ‘0’ at the beginning of Client transmission; automatically cleared to ‘0’ at the end of Client reception.
  2. Automatically cleared to ‘0’ at the beginning of Client transmission.

Legend: HC = Hardware Clearable bit

Name: I2CxCONL
Offset: 0x200, 0x21C, 0xF5C

Bit 15141312111098 
 I2CEN I2CSIDLSCLRELSTRICTA10MDISSLWSMEN 
Access R/WR/W/HCR/WR/WR/WR/WR/W 
Reset 0010000 
Bit 76543210 
 GCENSTRENACKDTACKENRCENPENRSENSEN 
Access R/WR/WR/WR/W/HCR/W/HCR/W/HCR/W/HCR/W/HC 
Reset 00000000 

Bit 15 – I2CEN I2Cx Enable bit (writable from software only)

ValueDescription
1

Enables the I2Cx module, and configures the SDAx and SCLx pins as serial port pins

0

Disables the I2Cx module; all I2C pins are controlled by port functions

Bit 13 – I2CSIDL I2Cx Stop in Idle Mode bit

ValueDescription
1

Discontinues module operation when device enters Idle mode

0

Continues module operation in Idle mode

Bit 12 – SCLREL  SCLx Release Control bit (I2C Client mode only)(1)

If STREN = 1:(2)

User software may write ‘0’ to initiate a clock stretch and write ‘1’ to release the clock. Hardware clears at the beginning of every Client data byte transmission. Hardware clears at the end of every Client address byte reception. Hardware clears at the end of every Client data byte reception.

If STREN = 0:

User software may only write ‘1’ to release the clock. Hardware clears at the beginning of every Client data byte transmission. Hardware clears at the end of every Client address byte reception.

ValueDescription
1

Releases the SCLx clock

0

Holds the SCLx clock low (clock stretch)

Bit 11 – STRICT I2Cx Strict Reserved Address Rule Enable bit

ValueDescription
1

Strict reserved addressing is enforced; for reserved addresses.

(In Client Mode) – The device doesn’t respond to reserved address space and addresses falling in that category are NACKed.

(In Host Mode) – The device is allowed to generate addresses with reserved address space.

0

Reserved addressing would be Acknowledged.

(In Client Mode) – The device will respond to an address falling in the reserved address space. When there is a match with any of the reserved addresses, the device will generate an ACK.

(In Host Mode) – Reserved.

Bit 10 – A10M 10-Bit Client Address Flag bit

ValueDescription
1

I2CxADD is a 10-bit Client address

0

I2CxADD is a 7-bit Client address

Bit 9 – DISSLW Slew Rate Control Disable bit

ValueDescription
1

Slew rate control is disabled for Standard Speed mode (100 kHz, also disabled for 1 MHz mode)

0

Slew rate control is enabled for High-Speed mode (400 kHz)

Bit 8 – SMEN SMBus Input Levels Enable bit

ValueDescription
1 Enables input logic so thresholds are compliant with the SMBus specification
0 Disables SMBus-specific inputs

Bit 7 – GCEN  General Call Enable bit (in I2C Client mode only)

ValueDescription
1 Enables interrupt when a general call address is received in I2CxRSR; module is enabled for reception
0 General call address is disabled.

Bit 6 – STREN SCLx Clock Stretch Enable bit

In I2C Client mode only; used in conjunction with the SCLREL bit.

ValueDescription
1

Enables clock stretching

0

Disables clock stretching

Bit 5 – ACKDT Acknowledge Data bit

In I2C Host mode during Host Receive mode. The value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.

In I2C Client mode when AHEN = 1 or DHEN = 1. The value that the Client will transmit when it initiates an Acknowledge sequence at the end of an address or data reception.

ValueDescription
1

NACK is sent

0

ACK is sent

Bit 4 – ACKEN Acknowledge Sequence Enable bit

In I2C Host mode only; applicable during Host Receive mode.

ValueDescription
1

Initiates Acknowledge sequence on SDAx and SCLx pins, and transmits ACKDT data bit

0

Acknowledge sequence is Idle

Bit 3 – RCEN  Receive Enable bit (in I2C Host mode only)

ValueDescription
1

Enables Receive mode for I2C; automatically cleared by hardware at end of 8-bit receive data byte

0

Receive sequence is not in progress

Bit 2 – PEN  Stop Condition Enable bit (in I2C Host mode only)

ValueDescription
1

Initiates Stop condition on SDAx and SCLx pins

0

Stop condition is Idle

Bit 1 – RSEN  Restart Condition Enable bit (in I2C Host mode only)

ValueDescription
1

Initiates Restart condition on SDAx and SCLx pins

0

Restart condition is Idle

Bit 0 – SEN  Start Condition Enable bit (in I2C Host mode only)

ValueDescription
1

Initiates Start condition on SDAx and SCLx pins

0

Start condition is Idle