3.10.7.3.1.5 T2IMR – Timer2
Interrupt Mask Register
| Name: | T2IMR |
| Offset: | 0x076 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | | T2CIM | T2OIM | |
| Access | R | R | R | R | R | R | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved
Bit
This bit is reserved and read
as ‘0’.
Bit 6 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 5 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 4 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 3 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 2 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 1 – T2CIM Timer2 Compare
Interrupt Mask
If the T2CIM bit is written to
‘1’ and the I bit in SREG is set, the Timer2 compare match
interrupt is enabled. The corresponding interrupt is executed if a compare match
occurs, for example, when the T2COF bit is set in the Timer2 interrupt flag register
(T2IFR).
Bit 0 – T2OIM Timer2 Overflow
Interrupt Mask
If the T2OIM bit is written to
‘1’ and the I bit in SREG is set (‘1’), the
Timer2 overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer2 occurs, i.e., when the T2OFF bit is set in the Timer2 Interrupt
Flag Register (T2IFR).
