3.10.7.3.1.4 T2IFR – Timer2
Interrupt Flag Register
| Name: | T2IFR |
| Offset: | 0x016 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | | T2COF | T2OFF | |
| Access | R | R | R | R | R | R | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 6 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 5 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 4 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 3 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 2 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 1 – T2COF Timer2 Compare
Flag
This flag is set to
‘1’ during the clock cycle after the counter value matches the
compare register. The flag (T2COF) is cleared when the interrupt routine is
executed. Alternatively, the flag can be cleared by writing a logical
‘1’ to it.
Bit 0 – T2OFF Timer2 Overflow
Flag
This flag is set by the T2OVF
signal when the counter reaches its maximum value (0xFF). If the I-bit in SREG and
the T2OIM bit are set in T2IMR, the MCU jumps to the corresponding interrupt vector.
The flag is cleared when the interrupt routine is executed. Alternatively, the flag
can be cleared by writing a logical ‘1’ to
it.
