3.10.7.3.1.6 T2MR – Timer 2 Mode Register

Name:	T2MR
Offset:	0x075
Reset:	0x00

This register must only be modified while the timer is disabled (T2CR.T2ENA = 0). Modifying the bits during operation leads to unpredictable operation.


Bit	7	6	5	4	3	2	1	0
	T2DC[1:0]		T2PS[3:0]				T2CS[1:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 7:6 – T2DC[1:0] Timer2 Duty Cycle

The T2DC[1:0] bits select the duty cycle mode of the duty cycle generator as shown in the following table.

Table 3-92. Timer2 Duty Cycle Bit Description
T2DC1	T2DC0	Function of the Duty Cycle Generator	Additional Divider Effect
`0`	`0`	Bypassed (DCG0)	1
`0`	`1`	Duty cycle 1/1 (DCG1)	2
`1`	`0`	Duty cycle 1/2 (DCG2)	3
`1`	`1`	Duty cycle 1/3 (DCG3)	4

Bits 5:2 – T2PS[3:0] Timer2 Prescaler Select

The T2PS[3:0] bits select the prescaler value of Timer2 as shown in the following formula:

p r e s c a l e r V a l u e = 2^{T 2 P S [3 : 0]} ......(49)

{C L 2 P}_{F r e q u e n c y} = \frac{{C L 2}_{F r e q u e n c y}}{p r e s c a l e r V a l u e} = \frac{{C L 2}_{F r e q u e n c y}}{2^{T 2 P S [3 : 0]}} ......(50)

T2PS[3:0] ∈ {0..15}

Bits 1:0 – T2CS[1:0] Timer 2 Clock Select

The T2CS[1:0] bits select the input clock (CL2) of Timer2 as shown in the following table.

Table 3-93. Timer2 Input Clock Select Bit Description
T2CS[1:0]		Input Clock (CL2) of Timer
`0`	`0`	CLK_SRC
`0`	`1`	CLK_VDIV
`1`	`0`	CLK_T
`1`	`1`	CLK_XTO4