3.10.7.3.1.1 T2CR – Timer2 Control Register

Name: T2CR
Offset: 0x012
Reset: 0x00

Bit 76543210 
 T2ENAT2TOST2REST2TOPT2CRMT2CTMT2OTM 
Access R/WR/WWR/WRR/WR/WR/W 
Reset 00000000 

Bit 7 – T2ENA Timer2 Enable

This bit controls the Timer2 block. The T2ENA bit must be written to logic ‘1’ to enable Timer2. If the T2ENA bit is written to logic ‘0’, Timer2 is disabled. Reading this bit shows the actual state of Timer2. Because internal synchronization requires 2½ asynchronous CL2 clock cycles to enable or disable Timer2, it may take some time to read a logic ‘1’ after having enabled Timer2. The same applies for disabling.

Care has to be taken if the T2ENA or T2CR register is written by consecutive cbi/sbi instructions. For example, clearing the T2ENA bit with a cbi instruction followed by a cbi/sbi instruction on another bit of the T2CR re-enables the timer. (The read-modify-write sequence is still reading the T2ENA = 1 and writing it back, thus, enabling the timer.)

The asynchronous clock can be forced on without synchronization by writing a logic ‘1’ to the T2ENA bit twice within four AVR clock cycles. This can be useful for slow clocks, for example, when the first edge of a newly enabled oscillator leads to an increased counter value.

Bit 6 – T2TOS Timer2 Toggle with Start

The T2TOS bit must be written to logic ‘1’ if the modulator output of Timer2 must be toggled when the timer is enabled with T2ENA. If the T2TOS bit is written to logic ‘0’, the modulator output of Timer2 is not toggled with the timer enable.

Bit 5 – T2RES Timer2 Reset

The T2RES bit can be written to logic ‘1’ to reset the prescaler and counter. This is only allowed if the timer is stopped (T2ENA = 0). The T2RES bit is automatically cleared one cycle after the write.

Bit 4 – T2TOP Timer2 Toggle Output Preset

The T2TOP bit must be written to logic ‘1’ to set the toggle flip-flop. Clearing the T2TOP resets the toggle flip-flop. This bit allows the programmer to preset the toggle output flip-flop in the modulator of Timer2. If the timer is stopped, this bit shows the actual value of the toggle flip-flop.
Note: If T2ENA = 1, no output preset is possible.

Bit 3 –  Reserved Bit

This bit is reserved and reads as ‘0’.

Bit 2 – T2CRM Timer2 Compare Reset Mask

The T2CRM bit must be written to logic ‘1’ to enable the counter reset if a match of the counter with the compare register occurs. If the T2CRM bit is written to logic ‘0’, the counter reset is disabled.

Bit 1 – T2CTM Timer2 Compare Toggle Mask

The T2CTM bit must be written to logic ‘1’ to enable the compare toggle. If the T2CTM bit is written to logic ‘0’, the compare toggle is disabled. A match of the counter with the compare register generates an output clock of the counter (CLKT2).

Bit 0 – T2OTM Timer2 Overflow Toggle Mask

The T2OTM bit must be written to logic ‘1’ to enable the overflow toggle. If the T2OTM bit is written to logic ‘0’, the overflow toggle is disabled. A counter overflow generates an output clock of the counter (CLKT2).