13.18.3 Sleep Mode

Sleep mode is entered when both a SLEEP command is sent to the device via DE2 communications and the OE pin is low. The SLEEP bit in the CFG0 Configuration register indicates when the device should transition to a low-power mode. The device will operate normally until the OE pin is transitioned low by an external device. At that point in time, the SLEEP bit value determines whether the device transitions to Standby mode or low-power Sleep mode. The Supply Current (I_SUP) during Sleep mode will typically be 5 μA. When Sleep mode is activated, most functions will be shut off, including the V_REG LDO. Only the Power-on Reset monitor and minimal state machine will remain active to detect a wake-up event. This indicates that the host processor will be shut down if the host is using the V_REG LDO regulator for power. The device will stay in the low-power Sleep mode until either of the following conditions is met:

• The WAKE pin receives a signal corresponding with t_{WAKE_SETUP}. Table 13-1 specifies the signal conditions based on the device revision.

• Power is cycled.

The MOSFET Gate Driver is not required to retain configuration data while in Sleep mode. When exiting Sleep mode, the host should send a new configuration message to configure the device if the default configuration values are not desired. The same configuration sequence used during power-up may be used when exiting Sleep mode.

When activated, Sleep mode will always be entered regardless of any active Fault. This allows a transition to Sleep mode when the host is powered by the V_REG LDO and the regulator is in an unreliable state. The SLEEP bit in the Configuration register will be ignored at power-up until the system has enabled the V_REG LDO and the V_REG LDO has entered regulation.