11.1.3 Standard Capabilities

Name: OA_STDCAP
Address: 0x0002

Bit 3130292827262524 
  
Access RORORORORORORORO 
Reset ----0000 
Bit 2322212019181716 
  
Access RORORORORORORORO 
Reset 00000000 
Bit 15141312111098 
 TXFCSVCIPRACDPRAC 
Access RORORORORORORORO 
Reset 00000101 
Bit 76543210 
 CTCFTSCAIDCSEQCMINBPS[2:0] 
Access RORORORORORORORO 
Reset 11100101 

Bit 10 – TXFCSVC Transmit Frame Check Sequence Validation Capability

This bit indicates the ability for the MAC to validate the frame check sequence appended by and received from the SPI host. Frames received from the SPI host with an invalid frame check sequence will not be transmitted to the network.
Note: Transmit frame sequence validation is supported as indicated by this bit reading as ‘1’.
ValueDescription
0Transmit frame check sequence validation is not supported
1Transmit frame check sequence validation is supported

Bit 9 – IPRAC Indirect PHY Register access Capability

This bit indicates that the registers of the integrated PHY may be indirectly accessed using the optional OPEN Alliance MDIO Access 0-7 (MDIOACCn) registers.
Note: Indirect PHY register access via the optional OPEN Alliance MDIO Access 0-7 (MDIOACCn) is not supported and this bit always reads as ‘0’. PHY registers, however, may be accessed indirectly through the standard Clause 22 MMD Access Control (MMDCTRL) and MMD Access Address/Data (MMDAD) registers mapped directly into the SPI MMS0 register space.
ValueDescription
0Indirect PHY register access is not supported
1Indirect PHY register access is supported

Bit 8 – DPRAC Direct PHY Register Access Capability

This bit indicates that the integrated PHY registers are directly accessible in SPI MMS0 (Clause 22), MMS2 (PCS), MMS3 (PMA/PMD), and MMS4 (PHY vendor specific) as specified by the OPEN Alliance.
Note: PHY registers are directly accessible as indicated by this bit reading as ‘1’.
ValueDescription
0Direct PHY register access is not supported
1Direct PHY register access is supported

Bit 7 – CTC Cut-through Capability

This bit indicates the support for cut-through transfer of frames through the device to/from the network.
Note: Frame cut-through is supported as indicated by this bit reading as ‘1’.
ValueDescription
0Cut-through frame transfer is not supported
1Cut-through frame transfer is supported

Bit 6 – FTSC Frame Timestamp Capability

This bit indicates support for the capturing of timestamps on frame network ingress/egress.
Note: Frame ingress/egress timestamping is supported as indicated by this bit reading as ‘1’.
ValueDescription
0Timestamp capture on frame ingress/egress is not supported
1Timestamp capture on frame ingress/egress is supported

Bit 5 – AIDC Address Increment Disable Capability

This bit indicates support for disabling the automatic post-increment of the register address for control command reads and writes. When supported, disabling of the automatic address post-increment is done through the Automatic Increment Disable (AID) bit in the control command header.
Note: The register address auto-increment may be disabled as indicated by this bit reading as ‘1’.
ValueDescription
0Control command address post-increment disable is not supported
1Control command address post-increment disable is supported

Bit 4 – SEQC Transmit Data Block Sequence and Retry Capability

This bit indicates support for monitoring of the transmit data block header Sequence (SEQ) bit as sent by the host MCU.
Note: Transmit data block header Sequence bit (SEQ) is not supported as indicated by this bit reading as ‘0’.
ValueDescription
0Transmit data block header sequence monitoring is not supported
1Transmit data block header sequence monitoring is supported

Bits 2:0 – MINBPS[2:0] Minimum Block Payload Size Capability

This field indicates the minimum supported data block payload size. The minimum supported data payload size is 2N where N is the value of this bitfield.
Note: The minimum supported data payload size is 32 bytes as indicated by this field reading as ‘101’.
Note: This field is referred to as the Minimum Chunk Payload Size Capability (MINCPS) in the OPEN Alliance 10BASE‑T1x MAC‑PHY Serial Interface specification.
ValueDescription
011Minimum supported data payload size is 8 bytes
100Minimum supported data payload size is 16 bytes
101Minimum supported data payload size is 32 bytes
110Minimum supported data payload size is 64 bytes