11.1.17 Basic Control

Clause 22 Basic Control Register

Name:	BASIC_CONTROL
Address:	0xFF00


Bit	15	14	13	12	11	10	9	8
	SW_RESET	LOOPBACK	SPD_SEL[0]	AUTONEGEN	PD		REAUTONEG	DUPLEXMD
Access	R/W SC	R/W	RO	RO	R/W	R/W	RO	RO
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
		SPD_SEL[1]
Access	R/W	RO	RO	RO	RO	RO	RO	RO
Reset	0	0	0	0	0	0	0	0

Bit 15 – SW_RESET PHY Soft Reset

Writing a ‘1’ to this bit will initiate a software reset of the integrated PHY. A software reset will restore all integrated PHY registers to their default state, except for those fields identified as “NASR”, Not Affected by Software Reset.

Note: This bit is self-clearing. When setting this bit, do not set other bits in this register.

Value	Description
`0`	Normal operation
`1`	integrated PHY software reset

Bit 14 – LOOPBACK Near-End Loopback

When set, this bit enables a near-end loopback. When enabled, transmit data (TXD) pins from the MAC will be looped back onto the receive data (RXD) pins to the MAC. In this mode, no signal is transmitted onto the network media.

Important: PLCA must be disabled or configured as the PLCA Coordinator (Local ID = 0) when the near-end loopback mode is enabled.

Value	Description
`0`	Normal operation
`1`	Enable near-end loopback mode

Bit 13 – SPD_SEL[0] PHY Speed Select

Together with SPD_SEL[1], sets the network communication speed.

Note: Only 10 Mbit/s is supported. This bit is always ‘0’.

Value	Description
`00`	10 Mbit/s
`01`	100 Mbit/s
`10`	1000 Mbit/s
`11`	Reserved

Bit 12 – AUTONEGEN Auto-Negotiation Enable

Note: Auto-negotiation is not supported. This bit is always ‘0’.

Value	Description
`0`	Disable auto-negotiate process
`1`	Enable auto-negotiate process

Bit 11 – PD Power Down

Setting this bit will power down the PMA transceiver leaving the remainder of the device functional.

Note: This bit is the same as the Low Power Enable bit in the 10BASE-T1S PMA Control register.

Value	Description
`0`	Normal operation
`1`	PMA will be powered down

Bit 9 – REAUTONEG Restart Auto-Negotiation

Note: Auto-negotiation is not supported. This bit is always ‘0’.

Value	Description
`0`	Normal operation
`1`	Restart auto-negotiate process

Bit 8 – DUPLEXMD Duplex Mode

This bit configures the PHY for full-duplex or half-duplex network communication.

Note: Only half duplex operation is supported. This bit is always ‘0’.

Value	Description
`0`	Half duplex
`1`	Full duplex

Bit 6 – SPD_SEL[1] PHY Speed Select

See description for SPD_SEL[0] for details.

Note: Only 10 Mbit/s operation is supported. This bit is always ‘0’.

LAN8650/1