LAN8650/1

11.1.4 Reset Control and Status Register

Name:	OA_RESET
Address:	0x03


Bit	31	30	29	28	27	26	25	24

Access	RO	RO	RO	RO	RO	RO	RO	RO
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16

Access	RO	RO	RO	RO	RO	RO	RO	RO
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8

Access	RO	RO	RO	RO	RO	RO	RO	RO
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
								SWRESET
Access	RO	RO	RO	RO	RO	RO	RO	R/W SC
Reset	0	0	0	0	0	0	0	0

Bit 0 – SWRESET Software Reset

Writing a ‘1’ to this bit will fully reset the device including the integrated PHY. When set, the reset will not occur until the CS_N pin has been deasserted high following the SPI transaction performing the write.

Note: This bit is self clearing upon reset of the device.

Value	Description
`0`	Normal operation
`1`	Device performs a reset

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