11.1.5 Configuration 0 Register

Name:	OA_CONFIG0
Address:	0x004


Bit	31	30	29	28	27	26	25	24

Access	RO	RO	RO	RO	RO	RO	RO	RO
Reset	-	-	-	-	0	0	0	0


Bit	23	22	21	20	19	18	17	16

Access	RO	RO	RO	RO	RO	RO	RO	RO
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	SYNC	TXFCSVE	RFA[1:0]		TXCTHRESH[1:0]		TXCTE	RXCTE
Access	R/W1S	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	FTSE	FTSS	PROTE	SEQE		BPS[2:0]
Access	R/W	R/W	R/W	RO	RO	R/W	R/W	R/W
Reset	0	0	0	0	0	1	1	0

Bit 15 – SYNC Configuration Synchronization

Once the device has been configured and is ready for Ethernet frames to be transferred between the network and SPI, the host MCU sets this bit to a ‘1’. This bit is reflected in the data footer SYNC bit.

Note: Once set, this bit may only be cleared by a reset of the device.

Value	Description
`0`	Device has not been configured and transfer of Ethernet frames is not permitted
`1`	Device has been configured and transfer of Ethernet frames may occur

Bit 14 – TXFCSVE Transmit Frame Check Sequence Validation Enable

When this bit is set, the MAC will interpret the final four bytes of frames received from the SPI host as an Ethernet frame check sequence. The MAC will validate the received frame to verify correct reception via SPI. Should an error be detected in the frame received from the host over SPI, the device will drop the frame and not transmit it onto the network.

Note: When enabling this feature, the SPI host must pad the frame to the minimum size and append the calculated 32‑bit frame check sequence.

Value	Description
`0`	Transmit frame check sequence validation is not performed. The internal MAC will pad frames received from the host to the minimum packet size and append the correct frame check sequence prior to transmitting the packet onto the network.
`1`	Transmit frame check sequence validation is performed. The SPI host must pad all frames to the minimum packet size and append the correct frame check sequence. The internal MAC will validate the frame received from the host before transmitting it onto the network.

Bits 13:12 – RFA[1:0] Receive Frame Alignment

This field configures the alignment of receive frames within the receive data blocks. When this field is ‘00’, receive Ethernet frames may begin at any word of any receive SPI data block payload.

When this field is ‘01’, the start of all receive Ethernet frames will be output to the SPI aligned to the beginning of any receive data block payload with a Start Word Offset (SWO) of zero.

When this field is configured to ‘10’, the start of all receive Ethernet frames will be output to the SPI beginning with the first receive data block payload following CS_N assertion. The Start Word Offset (SWO) will always be zero. Only one frame may be received per assertion of CS_N.

Note: Writing this field to ‘11’ is invalid and will result in undefined operation.

Value	Description
`00`	Receive Ethernet frames may begin at any word of any receive data block. (Default)
`01`	Zero-Align Receive Frame Enable (ZARFE) Receive Ethernet frames will begin only at the first word of the receive data payload in any data block.
`10`	CS_N Align Receive Frame Enable (CSARFE) Receive Ethernet frames only begin in the first word of the first receive data block payload following assertion of CS_N
`11`	Invalid

Bits 11:10 – TXCTHRESH[1:0] Transmit Credit Threshold

This field configures the minimum number of transmit credits (TXC) of free buffers that must be available within the device before IRQ_N will be asserted. This guarantees a minimum number of Ethernet frame data blocks the SPI host may send to the device in a burst.

Value	Description
`00`	IRQ_N will be asserted when enough buffer space is available for at least 1 data block
`01`	IRQ_N will be asserted when enough buffer space is available for at least 4 data blocks
`10`	IRQ_N will be asserted when enough buffer space is available for at least 8 data blocks
`11`	IRQ_N will be asserted when enough buffer space is available for at least 16 data blocks

Bit 9 – TXCTE Transmit Cut-Through Enable

When set, this bit will enable the cut-through mode of egress frame transfer from the SPI to the network.

Value	Description
`0`	Transmit frame cut-through is disabled
`1`	Transmit frame cut-through is enabled

Bit 8 – RXCTE Receive Cut-Through Enable

When set, this bit will enable the cut-through mode of ingress frame transfer from the network to the SPI.

Value	Description
`0`	Receive frame cut-through is disabled
`1`	Receive frame cut-through is enabled

Bit 7 – FTSE Frame Timestamp Enable

When set, this bit enables the capturing of frame ingress/egress timestamps.

Value	Description
`0`	Frame ingress/egress timestamping is disabled
`1`	Frame ingress/egress timestamping is enabled

Bit 6 – FTSS Frame Timestamp Select

When frame timestamping is enabled (see FTSE), this bit selects the size and format of the timestamps added to the beginning of ingress frames and captured on request of egress frames.

Value	Description
`0`	32-bit timestamps
`1`	64-bit timestamps

Bit 5 – PROTE Control Data Read/Write Protection Enable

When set, this bit will enable the protection of control command register data against bit errors during transfer over the SPI.

Note: Control data read/write protection is disabled by default. Therefore, to enable control data read/write protection, this field must be initially written without write protection.

Value	Description
`0`	Control data read/write protection is disabled
`1`	Control data read/write protection is enabled

Bit 4 – SEQE Transmit data block header Sequence bit support Enable

If supported, setting this bit would enable the MAC-PHY monitoring of the Sequence (SEQ) bit sent by the SPI host in the transmit data block header.

Note: This feature is not supported. This bit is read-only and cannot be set.

Value	Description
`0`	Transmit data block header Sequence bit monitoring is disabled.
`1`	Transmit data block header Sequence bit monitoring is enabled. (Not supported)

Bits 2:0 – BPS[2:0] Block Payload Size

This field configures the receive and transmit data block payload size. The data payload size is configured to 2^N where N is the value of this bitfield.

Important: This field shall be changed prior to setting the Configuration Synchronization (SYNC) bit in this register enabling Ethernet packet transfer.

Important: When changing this field, the Buffer Size (BUFSZ) field in the Queue Transmit Configuration (QTXCFG) and Queue Receive Configuration (QRXCFG) must also be changed.

Note: This field is referred to as the Chunk Payload Size Capability (CPS) in the OPEN Alliance 10BASE‑T1x MAC‑PHY Serial Interface specification.

Value	Description
`101`	32 byte data block payload size
`110`	64 byte data block payload size (default)
`others`	Reserved

LAN8650/1